High-performance multiply-accumulate unit by integrating binary carry select adder and counter-based modular wallace tree multiplier for embedding system

Abstract

Multiply-Accumulate (MAC) units have been developed recently for various high-performance applications. A crucial component of computing devices, particularly embedded systems, is the MAC unit. The fundamental MAC unit is composed of Multiplier, Adder, and Accumulator. The input for the MAC unit is read from memory cells and given to the MAC multiplier block that multiplies the inputs and passes the result to an adder, which stores the result in memory. One clock cycle is required to complete the full operation. In this manuscript, a lesser power higher speed MAC unit is proposed for Embedding system. High speed binary carry select adders are utilized in MAC units for their speed and integration with three different blocks includes half sum with carry generators (HSCG), final carry generators (FCG), and final sum generators (FSG). For Multiplier design in MAC unit, the counter-based modular Wallace tree multiplier (CMWTM) is utilized, which has power-saving techniques. The proposed CMWTM-HSBCSA-ES MAC unit is implemented in Virtex FPGA development board utilizing Verilog programming language in Xilinx ISE 14.5 design tools. The efficacy of proposed design can be assessed with the metrics such as area, delay, dynamic power consumption, energy, normalized energy and speed. Then the performance of the proposed design provides 16.58%, 41.57% and 25.44% higher speed, 50%, 3.08% and 36% lower delay and 28.03%, 24.50% and 50.32% lower energy compared with the existing MAC unit designs, such as AxMAC-ES, a higher performance MAC unit through incorporating additions with accumulations into partial product reduction procedure (PPR-BA-ES) and high-accuracy MAC technique for unary stochastic computing (TE–SC–ES) respectively.