Design of Baugh Wooley and Wallace tree multiplier using two phase clocked adibatic static CMOS logic

Abstract

In this paper the low power operation of Baugh wooley multiplier and Wallace tree multiplier are discussed. The circuits are implemented using two phase clocked adiabatic static CMOS logic (2PASCL) and the power consumption of these circuits is compared with those of static CMOS logic. Baugh Wooley multiplier is implemented using three different designs. The circuits are implemented in 45nm CMOS process technology and the comparison result shows that Wallace tree Multiplier shows less power consumption compared to Baugh wooley multiplier and the power consumption is reduced by 62.66% for Wallace tree multiplier compared to static CMOS logic.