Design of Low-Power Square Root Carry Select Adder and Wallace Tree Multiplier Using Adiabatic Logic

Abstract

Power dissipation is a significant issue in many digital and VLSI systems. Adiabatic logic is a promising technique in minimizing the power dissipation, and positive feedback adiabatic logic (PFAL) proves to be efficient. The arithmetic operations in the digital systems are incomplete without the use of adders and multipliers. In this paper, a 16-bit square root carry select adder (SQRT CSLA) is implemented using ripple carry adder (RCA). The limitation of power and area in SQRT CSLA using RCA is overcome by incorporating Binary to Excess-1 Converter (BEC) in place of RCA. An 8 × 8 Wallace tree multiplier (WTM) is implemented using the concept of carry-save addition. The limitation of area in WTM is overcome by implementing reduced complexity WTM (RCWTM). The adders and multipliers are realized in both static CMOS and PFAL in Cadence Virtuoso 180 nm technology and simulated in Spectre. The static CMOS-based SQRT CSLA using BEC dissipates 50.25% less power as compared to SQRT CSLA using RCA which makes SQRT CSLA using BEC a better choice w.r.t. power dissipation and area. The PFAL-based SQRT CSLA using RCA and SQRT CSLA using BEC dissipates 54.5 and 83.5% less power as compared to static CMOS designs. PFAL-based RCWTM dissipates 81.8% less power than the static CMOS design. Circuits designed using PFAL dissipates less power as compared to those designed using static CMOS logic with a tradeoff in area.