High Level Synthesis for Retiming Stochastic VLSI Signal Processing Architectures

Abstract

With high integration density due to scaling of IC fabrication processes, faster design cycles, are the need of today along with development of energy efficient architectures fulfilling the speed requirements. The focus here is the to build up features of stochastic computing for data centric or data steaming applications. High level synthesis (HLS) allows the designer to incorporate transformations on the applications before the register transfer level (RTL) generation to incorporate design space explorations. Herein the design space explorations start with retiming. Also the novelty is that filter bench marks considered are implemented by incorporating stochastic computing functions. The same are used to develop the filter benchmarks and then retiming transformation is applied in HLS. The design space trade off results with respect to retiming transformations on conventional computation and stochastic computing architectures are presented, for area and power and it is found that stochastic computing results in area saving and power saving scales relatively for higher order applications namely the filter benchmarks showing that stochastic structures to be energy efficient than conventional computing. The future scope of the work is to consider accuracy analysis based on end user demand of accuracy versus energy efficiency.