Signal Processing Architecture Research Articles

Efficient Audio Filter Using Folded Pipelining Architecture Based on Retiming Using Evolutionary Computation

It is important in digital signal processing (DSP) architectures to minimize the silicon area of the integrated circuits. This can be achieved by reducing the number of functional units such as adders and multipliers. In literature, folding technique is used to reduce the functional units by executing multiple algorithm operations on a single functional unit. Register minimization techniques are used to reduce the number of registers in a folded architecture. Retiming is a technique that needs to be performed before applying folding. In this paper, retiming is performed based on nature inspired evolutionary computation method. This technique generates the database of solutions from which best solution can be picked for folding further. As a part of this work, an efficient folded noise removal audio filter prototype is designed as an application example using evolutionary computation-based retiming and folding with register minimization. Folding technique will however increase the number of registers while multiplexing datapath adder and multiplier elements. Register minimization technique is used after folding to reduce the number of registers. After obtaining retimed, folded filter architecture, low level synthesis is performed which involves mapping of datapath adder and multiplier blocks to actual hardware. Various architectures of adders and multipliers are compared in area-power-performance space and depending on the user defined constraint, folded architecture with specific combination of data path elements is mapped on to hardware. A framework is designed in this paper to automate the entire process which reduces the design cycle time. All the designed filters are targeted for ASIC implementation. The results are compared and are provided as part of simulation results.

Cost-Effective and Variable-Channel FastICA Hardware Architecture and Implementation for EEG Signal Processing

This paper proposes a cost-effective and variable-channel floating-point fast independent component analysis (FastICA) hardware architecture and implementation for EEG signal processing. The Gram-Schmidt orthonormalization based whitening process is utilized to eliminate the use of the dedicated hardware for eigenvalue decomposition (EVD) in the FastICA algorithm. The proposed two processing units, PU1 and PU2, in the presented FastICA hardware architecture can be reused for the centering operation of preprocessing and the updating step of the fixed-point algorithm of the FastICA algorithm, and PU1 is reused for Gram-Schmidt orthonormalization operation of preprocessing and fixed-point algorithm to reduce the hardware cost and support 2-to-16 channel FastICA. Apart from the FastICA processing, the proposed hardware architecture supports re-reference, synchronized average, and moving average functions. The cost-effective and variable-channel FastICA hardware architecture is implemented in 90 nm 1P9M complementary metal-oxide-semiconductor (CMOS) process. As a result, the FastICA hardware implementation consumes 19.4 mW at 100 MHz with a 1.0 V supply voltage. The core size of the chip is 1.43 mm2. From the experimental results, the presented work achieves satisfactory performance for each function.

Power and quality-aware image processing soft-resilience using online multi-objective GAs

A self-aware signal processing architecture is proposed based on adaptive resource escalation which is guided by a multi-objective genetic algorithm (GA). The GA prioritises tasks within a reconfigurable hardware fabric to maintain the quality-of-service and power consumption objectives. Attainment of these objectives is subject to the intrinsic reliability and performance of the computational elements in the resource pool. A health metric at the application layer, such as peak-signal-to-noise ratio (PSNR) measurement in a discrete cosine transform (DCT) or measure of confidence in a support vector machine (SVM) classifier, is used to assess throughput performance. When performance decreases beyond acceptable tolerances, the primary objective is to maximally recover output quality. The secondary objective is to minimise power consumption which also depends upon the input signal characteristics, in addition to the utilised computational resources. An adaptive guidance function for GA-driven recovery is proposed and validated for these objectives. It retains healthy processing elements in the throughput data path to gracefully-degrade throughput by optimising resource selection.

IJARCCE - Computer and Communication Engineering

2 Abstract: Multiplication is one of the most critical arithmetic operation, which is extensively used in many VLSI systems such as application specific based digital signal processor architectures and microprocessor. Multipliers are the major source of power dissipation in the VLSI systems. By reducing the power consumption of the multipliers the power consumption of the VLSI system can be reduced. This paper presents the CLRCL full adder based 4*4 Wallace and Dadda multipliers. The CLRCL full adder has only ten transistors which is less in number when compared with conventional full adders which is used to design these multipliers. Designing Wallace and Dadda multiplier by using CLRCL full adder will reduce the transistor count and power consumption. The proposed design is simulated using 0.12µm.

Multiplierless Design of Folded DSP Blocks

This article addresses the problem of minimizing the implementation cost of the time-multiplexed constant multiplication (TMCM) operation that realizes the multiplication of an input variable by a single constant selected from a set of multiple constants at a time. It presents an efficient algorithm, called orpheus , that finds a multiplierless TMCM design by sharing logic operators, namely adders, subtractors, adders/subtractors, and multiplexors (MUXes). Moreover, this article introduces folded design architectures for the digital signal processing (DSP) blocks, such as finite impulse response (FIR) filters and linear DSP transforms, and describes how these folded DSP blocks can be efficiently realized using TMCM operations optimized by orpheus . Experimental results indicate that orpheus can find better solutions than existing TMCM algorithms, yielding TMCM designs requiring less area. They also show that the folded architectures lead to alternative designs with significantly less area, but incurring an increase in latency and energy consumption, compared to the parallel architecture.

Functional self-test of high-performance pipe-lined signal processing architectures

We propose a new methodology for Built-In Self-Test (BIST) where contrary to the traditional scan-path based Logic BIST, the proposed solution for test generation does not need any additional hardware, and will not have any impact on the working performance of the system. A class of digital systems organized as pipe-lined signal processing architectures is targeted. The on-line generated signal data used for processing in the system serve as test pattern sources. Testing under normal working conditions and with typically processed data, allows exercising of the system on-line and at-speed, facilitating the detection of dynamic faults like delays and cross-talks to achieve high test quality. The proposed new self-test method is free from the negative aspect of over-testing, compared to the traditional Logic BIST approaches, and uses minimal amount of added hardware. Experimental research was based on the case study of specialized bio-signal processor architecture. The experiments showed promising results in reducing the cost of testing and achieving high fault coverage.

Highly efficient image registration for embedded systems using a distributed multicore DSP architecture

We present a complete approach to highly efficient image registration for embedded systems, covering all steps from theory to practice. An optimization-based image registration algorithm using a least-squares data term is implemented on an embedded distributed multicore digital signal processor (DSP) architecture. All relevant parts are optimized, ranging from mathematics, algorithmics, and data transfer to hardware architecture and electronic components. The optimization for the rigid alignment of two-dimensional images is performed in a multilevel Gauss–Newton minimization framework. We propose a reformulation of the necessary derivative computations, which eliminates all sparse matrix operations and allows for parallel, memory-efficient computation. The pixelwise parallellism forms an ideal starting point for our implementation on a multicore, multichip DSP architecture. The reduction of data transfer to the particular DSP chips is key for an efficient calculation. By determining worst cases for the subimages needed on each DSP, we can substantially reduce data transfer and memory requirements. This is accompanied by a sophisticated padding mechanism that eliminates pipeline hazards and speeds up the generation of the multilevel pyramid. Finally, we present a reference hardware architecture consisting of four TI C6678 DSPs with eight cores each. We show that it is possible to register high-resolution images within milliseconds on an embedded device. In our example, we register two images with 4096 × 4096 pixels within 93 ms, while off-loading the CPU by a factor of 20 and requiring 3.12 times less electrical energy.

Multicarrier Offset-QAM for Long-Haul Coherent Optical Communications

The availability of high-speed digital-to-analog converters for coherent optical communication systems makes it possible to digitally divide the available electrical bandwidth into subchannels on each optical carrier which enables a parallel implementation of the digital signal processing. In this paper, we use electrical multicarrier offset-QAM modulations to achieve crosstalk-free modulation for subcarriers spaced at the symbol rate. We show that in coherent optical communication systems, several impairments are bound to break the subcarrier orthogonality and cause failures of payload symbol recovering. We propose a dedicated digital signal processing architecture which implements channel estimation and a new algorithm to track the phase in multicarrier offset-QAM modulation. We experimentally compare the latter with conventional multicarrier and single carrier QAM modulation so as to assess the benefits of crosstalk mitigation via offset-QAM modulation. We carry out experiments to test the transmission performance of multicarrier offset-QAM modulation in a dispersion-unmanaged long-haul transmission link.

Photonic circuits for iterative decoding of a class of low-density parity-check codes

Photonic circuits in which stateful components are coupled via guided electromagnetic fields are natural candidates for resource-efficient implementation of iterative stochastic algorithms based on propagation of information around a graph. Conversely, such message=passing algorithms suggest novel circuit architectures for signal processing and computation that are well matched to nanophotonic device physics. Here, we construct and analyze a quantum optical model of a photonic circuit for iterative decoding of a class of low-density parity-check (LDPC) codes called expander codes. Our circuit can be understood as an open quantum system whose autonomous dynamics map straightforwardly onto the subroutines of an LDPC decoding scheme, with several attractive features: it can operate in the ultra-low power regime of photonics in which quantum fluctuations become significant, it is robust to noise and component imperfections, it achieves comparable performance to known iterative algorithms for this class of codes, and it provides an instructive example of how nanophotonic cavity quantum electrodynamic components can enable useful new information technology even if the solid-state qubits on which they are based are heavily dephased and cannot support large-scale entanglement.

Towards a Standard Mixed-Signal Parallel Processing Architecture for Miniature and Microrobotics

The conventional analog-to-digital conversion (ADC) and digital signal processing (DSP) architecture has led to major advances in miniature and micro-systems technology over the past several decades. The outlook for these systems is significantly enhanced by advances in sensing, signal processing, communications and control, and the combination of these technologies enables autonomous robotics on the miniature to micro scales. In this article we look at trends in the combination of analog and digital (mixed-signal) processing, and consider a generalized sampling architecture. Employing a parallel analog basis expansion of the input signal, this scalable approach is adaptable and reconfigurable, and is suitable for a large variety of current and future applications in networking, perception, cognition, and control.

RIVER

For high-performance embedded hard-real-time systems, ASICs and FPGAs hold advantages over general-purpose processors and graphics accelerators (GPUs). However, developing signal processing architectures from scratch requires significant resources. Our design methodology is based on sets of configurable building blocks that provide storage, dataflow, computation, and control. Based on our building blocks, we generate hundreds of thousands of our dynamic streaming engine processors that we call DSEs. We store our DSEs in a repository that can be queried for (online) design space exploration. From this repository, DSEs can be downloaded and instantiated within milliseconds on FPGAs. If a loss of flexibility can be tolerated then ASIC implementations are feasible as well. In this article we focus on FPGA implementations. Our DSEs vary in cores, computational lanes, bitwidths, power consumption, and frequency. To the best of our knowledge we are the first to propose online design space exploration based on repositories of precompiled cores that are assembled of common building blocks. For demonstration purposes we map algorithms for image processing and financial mathematics to DSEs and compare the performance to existing highly optimized signal and graphics accelerators.

English

Technological advancements have resulted in significant changes in the processor architecture of mobile phones, transforming the typical mobile phones of 1990’s to modern smart phones. The next generation of mobile computing requirements will increase due to higher data rates, increased complexity algorithms, and greater computation diversity but the power requirements will be just as stringent to ensure reasonable battery lifetimes.The design of the next generation of mobile platforms must address three critical challenges: efficiency, programmability, and adaptivity. This paper presents analysis of mobile signal processing applications and advanced signal processing architectures to deal with the rigorous requirements. This paper illustrates the role of Digital Signal Processors for Third generation (3G) mobile systems and DSP architectures for 4G wireless communication.

A New Radar Signal Processing Architecture Based on Multi-Core Processor

Most radar systems based on the structure that contains many DSP chips. The system structure is always complex, and it is difficult to update. Nowadays, multi-core processor develops very fast. Compared with DSP chips, multi-core processor has better performance in signal processing field. In this paper, we present a signal processing architecture which based on multi-core processor. Pulse compression algorithms and PCI-E bus are discussed as two important technologies. Adaptive beamforming test results show that multi-core processor is able to achieve radar signal processing.

Real-Time Processing of Multifrequency Eddy Currents Testing Signals: Design, Implementation, and Evaluation

The design, implementation, and evaluation of a real-time digital signal processing architecture to generate and process multifrequency signals for eddy currents testing is described in this paper. This architecture is implemented on a dedicated instrument whose processing core is a field-programmable gate array. Stimulus generation is achieved using direct digital synthesis with some important improvements to reduce spurious frequency components. An in-phase and in-quadrature demodulation scheme is implemented to estimate the real and imaginary parts of the probe output signal. A cascaded integrator comb decimator is used to lower the sampling frequency and then allow narrowband filtering with low resources. The proposed architecture is able to generate and process the stimulus and input data at 125 MSamples/s and to estimate the input data components at 1.25 MSamples/s rate for eddy-currents with multiple simultaneous testing frequencies between 2.5 kHz and 10 MHz. Experimental validation is performed using a set of synthetic defects and two stimulus with different spectral composition.

English

In synthesizing Digital signal processing (DSP) architecture, maintaining low silicon area and high performance becomes an important factor which can be achieved by various optimization techniques. To achieve this, we employ two design optimization techniques: folding and retiming, which are applied to 3rd order Chebyshev I high pass digital filter to minimize the functional units (adders, multipliers) and to reduce the number of registers. Folding transformation is used to determine the control circuits in DSP architecture by executing multiple algorithm operation on a single functional unit. Retiming using register minimization is applied after folding, thereby reducing the numbers of multipliers and adders from 7 to 1 and 6 to 1, respectively, without affecting the input and output characteristics of the filter.   Key words: Data flow graph (DFG), Chebyshev filter, folding, retiming, lifetime analysis.

MIMO Signal Processing for Mode-Division Multiplexing: An overview of channel models and signal processing architectures

We present the fundamentals of multiple-input, multiple-output (MIMO) signal processing for mode-division multiplexing (MDM) in multimode fiber (MMF). As an introduction, we review current long-haul optical transmission systems and how continued traffic growth motivates study of new methods to increase transmission capacity per fiber. We describe the key characteristics of MIMO channels in MMF, contrasting these with wireless MIMO channels. We review MMF channel models, the statistics derived from them, and their implications for MDM system performance and complexity. We show that optimizing performance and complexity requires management of channel parameters-particularly group delay (GD) spread and mode-dependent loss and gain-by design of transmission fibers and optical amplifiers, and by control of mode coupling along the link. We describe a family of fibers optimized for low GD spread, which decreases with an increasing number of modes. We compare the performance and complexity of candidate MIMO signal processing architectures in a representative long-haul system design, and show that programmable frequency-domain equalization (FDE) of chromatic dispersion (CD) and adaptive FDE of modal dispersion (MD) is an attractive combination. We review two major algorithms for adaptive FDE of MD-least mean squares (LMS) and recursive least squares (RLS)-and analyze their complexity, throughput efficiency, and convergence time. We demonstrate that, with careful physical link design and judicious choice of signal processing architectures, it is possible to overcome MIMO signal processing challenges in MDM systems.

Special issue on design and architectures of real-time image processing in embedded systems

Current embedded systems are increasingly used to support high-performance applications. This is due to the diffusion of these systems in the domain of mobile devices and the need of a large number of services required from these systems. To support the execution of these applications, several architectures based on CPU, GPU or FPGA have been developed and are still under investigation. When the application demands both performance and flexibility, architectures based on several types of execution resources are of high benefit. In this context, designers define architectures which include all the necessary resources on the same chip, also called ‘‘Multiprocessor System on a Chip’’ (MPSoC). Image processing is one of the major applications in embedded domain, which requires high effort in computation. Image processing for medicine, automotive, and for video compression is the main algorithm that has been addressed by the authors of the Design and Architecture for Image and Signal Processing (DASIP) conference. This special issue presents several papers which address this general topic, and also presents papers dealing with the implementation complexity as well as exploring different opportunities concerning the possible architectures of CPU, GPGPU, FPGA and ASIC implementations. Comparisons among these different technologies are also presented in order to attempt defining the best implementation of the applications. Due to the complexities of the applications and architectures, research concerning methodologies for implementation is also addressed in this special issue. The main objective is to provide designers efficient methodologies and tools which can help during the exploration of different implementation opportunities. In the next paragraph, the guest editors provide a brief description of each paper presented in this special issue. We wish to have provided JRTIP readers a good reading collection and hope that these selected papers will be a source of inspiration for future works.

Quality Improvement and Power Reduction in Digital Signal Processing Using Approximate Adders

Digital Signal Processing (DSP) blocks are the backbone of all multimedia applications and Low Power is an imperative requirement for portable multimedia devices handling different signal processing algorithms and architectures. Human beings can capture useful information even if the output is having some error. Thus, we need not produce exact numerical outputs. Previous researches provide the error resiliency through Voltage Over Scaling (VOS) by various algorithms and architectures to reduce the errors. In this paper, the logic complexity reduction is proposed by using approximate adders which is obtained by reducing the number of transistors without reducing the quality of the output signal. Simulation results shows the power reduction by using approximate adders compared to the actual full adder cells.

Fast and robust software‐based digital phase‐locked loop for power electronics applications

In this study, a fast and fully software-based algorithm for digital phase-locked loop (PLL) is proposed via a new hybrid approach in software and hardware by using an advanced digital signal processor architecture. The proposed algorithm is robust against line disturbances such as phase-angle jump, voltage sag, third harmonic injection, multi-zero crossing and step change in frequency at the input voltage. Performance and robustness of the proposed method are investigated through experimental studies. Furthermore, it is compared with three different PLL algorithms in detail to show its superiority over existing methods.

Planar superconducting whispering gallery mode resonators

We introduce a microwave circuit architecture for quantum signal processing combining design principles borrowed from high-Q 3D resonators in the quantum regime and from planar structures fabricated with standard lithography. The resulting “2.5D” whispering-gallery mode resonators store 98% of their energy in vacuum. We have measured internal quality factors above 3 × 106 at the single photon level and have used the device as a materials’ characterization platform to place an upper bound on the surface resistance of thin film aluminum of less than 250 nΩ.