Signal Processing Architecture Research Articles

On the Use of Reciprocal Filter Against WiFi Packets for Passive Radar

This article derives a novel unified signal processing scheme for WiFi-based passive radar in order to limit its complexity and enhance its suitability for short range civilian applications. To this purpose, the exploitation of a reciprocal filtering (RpF) strategy is investigated as an alternative to conventional matched filtering at the range compression stage. Along with the well-known advantage of a remarkable sidelobes control capability for the resulting range-Doppler response, the use of a RpF is shown to provide additional benefits for the specific sensor subject of this article. Specifically, it allows to streamline the disturbance cancellation stage and to implement a unified signal processing architecture which is capable to handle the different modulation schemes typically adopted in WiFi transmissions. Appropriate adjustments are also proposed to the theoretical RpF in order to cope with the inherent loss in terms of signal-to-noise power ratio. The effectiveness of the proposed signal processing scheme encompassing the RpF strategy is proved against both simulated and experimental datasets.

Resource-Saving Customizable Pipeline Network Architecture for Multi-Signal Processing in Edge Devices.

With the development of the information age, the importance of edge computing has been highlighted in industrial site monitoring, health management, and fault diagnosis. Among them, the processing and computing of signals in edge scenarios is the cornerstone of realizing these scenarios. While the performance of edge devices has been dramatically improved, the demand for signal processing in the edge side has also ushered in explosive growth. However, the deployment of traditional serial or parallel signal processing architectures on edge devices has problems such as poor flexibility, low efficiency, and low resource utilization, making edge devices unable to exert their maximum performance. Therefore, this paper proposes a resource-saving customizable pipeline network architecture with a space-optimized resource allocation method and a coordinate addressing method for irregular topology. This architecture significantly improves the flexibility of multi-signal processing in edge devices, improves resource utilization, and further increases the performance potential of edge devices. Finally, we designed a comparative experiment to prove that the resource-saving and customizable pipeline network architecture can significantly reduce resource consumption under the premise of meeting real-time processing requirements.

Guest Editorial: Special Issue on Design and Architectures for Signal and Image Processing 2021

Guest Editorial: Special Issue on Design and Architectures for Signal and Image Processing 2021

All-Digital LoS MIMO With Low-Precision Analog-to-Digital Conversion

Line-of-sight (LoS) multi-input multi-output (MIMO) systems exhibit attractive scaling properties with increase in carrier frequency: for a fixed form factor and range, the spatial degrees of freedom increase quadratically for 2D arrays, in addition to the typically linear increase in available bandwidth. In this paper, we investigate whether modern all-digital baseband signal processing architectures can be devised for such regimes, given the difficulty of analog-to-digital conversion for large bandwidths. We propose low-precision quantizer designs and accompanying spatial demultiplexing algorithms, considering <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2 \times 2$ </tex-math></inline-formula> LoS MIMO with QPSK for analytical insight, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4 \times 4$ </tex-math></inline-formula> MIMO with QPSK and 16QAM for performance evaluation. Unlike prior work, channel state information is utilized only at the receiver (i.e., transmit precoding is not employed). We investigate quantizers with regular structure whose high-SNR mutual information approaches that of an unquantized system. We prove that amplitude-phase quantization is necessary to attain this benchmark; phase-only quantization falls short. We show that quantizers based on maximizing per-antenna output entropy perform better than standard Minimum Mean Squared Quantization Error (MMSQE) quantization. For spatial demultiplexing with severely quantized observations, we introduce the novel concept of virtual quantization which, combined with linear detection, provides reliable demodulation at significantly reduced complexity compared to maximum likelihood detection.

An FPGA-Based Upper-Limb Rehabilitation Device for Gesture Recognition and Motion Evaluation Using Multi-Task Recurrent Neural Networks

Upper-Extremity motor impairment affects millions of Americans due to cerebrovascular incidents, spinal cord injuries, or brain trauma. Current therapy practices used to assist these individuals in regaining motor functionality often require extensive time at rehabilitation facilities with potentially prohibitive travel or financial costs. This work presents a mobile low-cost field programmable gate array (FPGA)-smart rehabilitation system that can be used in home environments. The prototype is a rehabilitation table instrumented with a capacitive sensor array (CSA) to track upper-extremity motions of the user through proximity or touch. In addition, inertial measurement units (IMUs) are placed on the affected upper limb and combined with the CSA data with our sensor fusion signal processing architecture. Motions are classified and evaluated using multi-task convolutional recurrent neural networks with three additional motion quality output classes to personalize recognition based on the particular motor skills of each patient. The prototype achieves above 99&#x0025; accuracy with 32-bit fixed-point format implementation for recognizing dynamic motions and identifying unnatural characteristics (i.e., tremor or limited flexion and extension) in upper limb motions based on sensor values. The convolutional recurrent neural network (C-RNN) fusion classification network is implemented on a 200 MHz Zynq ZCU104 FPGA using an HLS-based design optimized with pipelining and parallelism techniques and achieves 5.4x speedup compared to ARM&#x00AE; Cortex-A53 implementation running at an operating frequency of 1.3 GHz. The prototype is also demonstrated to perform the machine learning classification in real-time.

Efficient Stochastic Computing FIR Filtering Using Sigma-Delta Modulated Signals

This work presents a soft-filtering digital signal processing architecture based on sigma-delta modulators and stochastic computing. A sigma-delta modulator converts the input high-resolution signal to a single-bit stream enabling filtering structures to be realized using stochastic computing’s negligible-area multipliers. Simulation in the spectral domain demonstrates the filter’s proper operation and its roll-off behavior, as well as the signal-to-noise ratio improvement using the sigma-delta modulator, compared to typical stochastic computing filter realizations. The proposed architecture’s hardware advantages are showcased with synthesis results for two FIR filters using FPGA and synopsys tools, while comparisons with standard stochastic computing-based hardware realizations, as well as with conventional binary ones, demonstrate its efficacy.

Advanced and versatile signal conditioning for GNSS receivers using the high‐rate DFT‐based data manipulator (HDDM)

<h3>Abstract</h3> Proper signal conditioning is crucial for reliable Global Navigation Satellite System (GNSS) navigation. Signal conditioning includes correcting receiver front-end distortions, shaping noise, removing interferences, and altering the received signal. The high-rate DFT-based data manipulator (HDDM) is a versatile signal processing architecture based on the Discrete Fourier Transform (DFT). In this article, the HDDM is theoretically modeled, analyzed, and evaluated. Some applications are presented, including interference mitigation, spectrum reconstruction, overlay signal design, altering signal modulations, and signal equalization. Additionally, the complexity of one concrete hardware implementation is investigated. The HDDM has shown excellent results with interference mitigation, and it can simultaneously achieve other signal conditioning tasks. Processing several tasks with the same nested architecture provides a significant processing benefit compared to discrete processing architectures. It emphasizes the benefits of a single architecture to simultaneously address several signal condition tasks, as opposed to separate structures requiring significantly more processing or poorer synergy.

Optical network design and analysis tools: A test of time

Telecom operators' infrastructure is sustained by optical communication networks that provide the means for exchanging large amounts of information, which is essential for many modern society needs. Optical networks are characterized by rapid breakthroughs in a variety of technologies. Relevantly, the last decade encompassed remarkable advances in optical networks’ subfields of signal processing, electronics, photonics, communications, protocols, and control-plane architectures. Hence, these advancements unlocked unprecedented transmission capacities, reconfigurability and programmability, entailing an evolution in the way which networks were designed, planned, and analyzed. In this paper, we review the historical status of optical planning and design tools by focusing on the major enabling technologies and relevant landmarks of the last decade(s). We begin by pinpointing the major breakthroughs in the optical data plane, estimation models capturing the transmission medium behavior and the control plane. We then distil the implications that these advancements entail in the landscape of optical network design and analysis tools, which commonly sit “on top” of the control plane or as a fully separated entity. Then, we speculate with our view for the future, in which automatic validation of optical network operations and dimensioning jointly with learning/artificial intelligence mechanisms will permit zero-touch optical networking: i.e. updating, provisioning, and upgrading network capacities, by means of automation with minimal human intervention. We conclude with a proposal of an architecture that encompasses data and control planes in a comprehensive manner for paving the way towards zero-touch optical networking.

Signal Processing Architecture for the HL-LHC Interaction Region BPMs

Signal Processing Architecture for the HL-LHC Interaction Region BPMs

A LOW POWER AND HIGH SPEED APPROXIMATE ADDER FOR IMAGE PROCESSING APPLICATIONS

Low power is an essential requirement for suitable multimedia devices, image compression techniques utilizing several signal processing architectures and algorithms. In numerous multimedia applications, human beings are able to congregate practical information from somewhat erroneous outputs. Therefore, exact outputs are not necessary to produce. In Digital signal processing system, adders play a vital role as an arithmetic module in fixing the power and area utilization of the system. The trade off parameters such as area, time and power utilization also the fault tolerance environment of few applications have employed as a base for the adverse development and use of approximate adders. In this paper, various types of existing adders, approximate adders are analyzed based on the area, delay and power consumption. Also an approximate, high speed and power efficient adder is proposed which yields the better performance than the existing adders. It can be used in various image processing applications, data mining and where the accurate outputs are not needed. The existing and proposed approximate adders are simulated by using Xilinx ISE for time and area utilization. Power simulation has been done by using Microwind Software.

Deep-Learning-Enhanced NOMA Transceiver Design for Massive MTC: Challenges, State of the Art, and Future Directions

Non-orthogonal multiple access (NOMA) is a promising evolution path to meet the requirements of massive machine type communications (mMTC) in 5G and beyond. However, the deployment of NOMA is hindered by the non-unified signal processing architectures of various NOMA schemes and the inflexibility resulting from the offline design paradigm. The block-wise optimized transceivers make its performance far from the limit. The recent breakthrough of deep learning and its positive applications to wireless communications have paved the way to tackle these challenges. This article studies the effectiveness and efficiency of deep learning in enhancing NOMA performance. Specifically, we first present the deep neural network (DNN), which is constructed via a uniform signal processing architecture, and use it as the unified multiuser receiver in both data and model-driven approaches. This enables the end-to-end optimization of NOMA transceivers due to the universal function approximation property of DNN. On the other hand, with DNN we can automatically extract the user access behaviors out of the time-series signals and optimize the transceivers to match these cross-lay-er behaviors. We further analyze the integration of non-orthogonal communication and neural computation to accomplish high-efficiency data transmission at low cost. Finally, we identify some essential future directions of deep-learning-enhanced NOMA from the perspectives of online reconfigurability and adaptability toward the ever changing environment in future mMTC.

An End-to-End Machine Learning based Unified Architecture for Non-Intrusive Load Monitoring

Non-Intrusive Load Monitoring (NILM) or load disaggregation aims to analyze power consumption by decomposing the energy measured at the aggregate level into constituent appliances level. The conventional load disaggregation framework consists of signal processing and machine learning-based pipelined architectures, respectively for explicit feature extraction and decision making. Manual feature selection in such load disaggregation frameworks leads to biased decisions that eventually reduce system performance. This paper presents an efficient End-to-End (E2E) approach-based unified architecture using Gated Recurrent Units (GRU) for NILM. The proposed approach eliminates explicit feature engineering and has a unified classification and prediction model for appliance power. This eventually reduces the computational cost and enhances response time. The performance of the proposed system is compared with conventional algorithms' with the use of recall, precision, accuracy, F1 score, the relative error in total energy and Mean Absolute Error (MAE). These evaluation metrics are calculated on the power consumption of top priority appliances of Reference Energy Disaggregation Dataset (REDD). The proposed architecture with an overall accuracy of 91.2 and MAE of 25.23 outperforms conventional methods for all electrical appliances. It has been showcased through a series of experiments that feature extraction and event-based approaches for NILM can readily be replaced with E2E deep learning techniques allowing simpler and cost-efficient implementation pathways.

A short review of some analog-to-digital converters resolution enhancement methods

The resolution of the analog-to-digital converter (ADC), i.e. the minimum voltage that ADC can recognize, is an important indicator of ADC performance. In order to improve the accuracy of ADCs, some approaches are proposed to enhance the resolution of ADC. This paper presents a review of ADC resolution enhancement schemes, which includes the introduction of primary features, the explanation of basic principles, as well as their merits, demerits, and trade-offs. It describes a variety of resolution enhancement schemes from different aspects such as signal processing, ADC calibration, and novel acquisition architectures, and analyzes their applicable scenes. Finally, some challenges and issues are briefly summarized, as well as some comments on future work in this field. By reviewing the current literature, we can make recommendations on the design of acquisition system resolution according to the actual requirements.

Low Complexity DSP for High Speed Optical Access Networking

A novel low-cost and energy-efficient approach for reaching 40 Gb/s signals is proposed for cost-sensitive optical access networks. Our proposed design is constituted of an innovative low-complex high-performance digital signal processing (DSP) architecture for pulse amplitude modulation (PAM-4), reuses existing commercial cost-effective 10-G components and eliminates the need of a power-hungry radio frequency (RF) component in the transmitter. Using a multi-functional 17-tap reconfigurable adaptive Volterra-based nonlinear equalizer with noise suppression, significant improvement in receiver optical power sensitivity is achieved. Results show that over 30 km of single-mode fiber (SMF) a link power budget of 33 dB is feasible at a bit-error-rate (BER) threshold of 10−3.

High Throughput Low Complexity and Low Power ePiBM RS Decoder Using Fractional Folding

This brief proposes a novel generalized Fractional Folding (FF) architecture for digital signal processing integrated circuits. With this new structure, a Fractional Folding based enhanced Parallel Inversionless Berlekamp-Massey (FF-ePIBM) Reed-Solomon Decoder is presented of which the number of processing element (PE) can be reduced to only one, resulting in ultra-low hardware complexity. The FF-ePIBM VLSI architecture can greatly reduce the hardware cost by about 60% compare to the fully expanded parallel ePIBM architecture. With FF-ePIBM architecture, syndrome calculation (SC) block and Chien search & error evaluation (CSEE) block are able to operate at a lower frequency resulting in about 14.8% power saving. A polyphase clock signal is needed in order to achieve fractional folding function according to specific fractional-factor. It is generated from Delay Locked Loop (DLL) at little or no extra cost in different SoCs. To maximize the throughput of decoder, pipelined architecture is adopted to optimize critical path delay. The RS (255, 239) decoder with FF-ePIBM architecture is finally implemented with 40nm CMOS technology. The synthesized results demonstrate that the decoder has a gate count of 12.9k and can operate at 3.1GHz to achieve a highest throughput of 24.8Gb/s and a best TSNT FoM value of 592 to this date.

Low communication parallel distributed adaptive signal processing (LC-PDASP) architecture for processing-inefficient platforms

Low communication parallel distributed adaptive signal processing (LC-PDASP) architecture for processing-inefficient platforms

Energy Efficient In-Memory Hyperdimensional Encoding for Spatio-Temporal Signal Processing

The emerging brain-inspired computing paradigm known as hyperdimensional computing (HDC) has been proven to provide a lightweight learning framework for various cognitive tasks compared to the widely used deep learning-based approaches. Spatio-temporal (ST) signal processing, which encompasses biosignals such as electromyography (EMG) and electroencephalography (EEG), is one family of applications that could benefit from an HDC-based learning framework. At the core of HDC lie manipulations and comparisons of large bit patterns, which are inherently ill-suited to conventional computing platforms based on the von-Neumann architecture. In this work, we propose an architecture for ST signal processing within the HDC framework using predominantly in-memory compute arrays. In particular, we introduce a methodology for the in-memory hyperdimensional encoding of ST data to be used together with an in-memory associative search module. We show that the in-memory HDC encoder for ST signals offers at least 1.80x energy efficiency gains, 3.36x area gains, as well as 9.74x throughput gains compared with a dedicated digital hardware implementation. At the same time it achieves a peak classification accuracy within 0.04% of that of the baseline HDC framework.

On the advancements of digital signal processing hardware and algorithms enabling the Origins Space Telescope

On August 22, 2019, the Origins Space Telescope (OST) Study Team delivered the OST Mission Concept Study Report and the OST Technology Development Plan to NASA Headquarters. A key component of this study report includes the technology roadmap for detector readout and how new radio frequency-system-on-chip (RFSoC)-based technology would be used to advance the far-infrared polarimeter instrument concept for a spaceflight mission. We present our current results as they pertain to the implementation of algorithms, hardware, and architecture for instrument signal processing of this proposed observatory using RFSoC technology. We also present a small case study, comparing a more conventional readout system with one based on the RFSoC and show a trade of system complexity versus technology readiness level.

Simplifying Single-Bin Discrete Fourier Transform Computations [Tips &amp;amp; Tricks

A digital signal processing (DSP) architecture is presented to compute single bins of the discrete Fourier transform (DFT) with low complexity. This architecture consists of a cascade of simple accumulators working at the input sampling rate and a polyphase finite impulse response (FIR) filter with complex coefficients working at a lower rate. The advantage of this structure is that, for several cases, it is possible to have a system with only one accumulator operating in the high-rate section and a low-order FIR filter working in the low-rate section. However, this depends on the index of the frequency bin to be computed (k) and the number of DFT points (N). Advantages and limitations of this approach are presented, and the implementation scheme is elaborated.

Design and Implementation of a Real-Time Multi-Beam Sonar System Based on FPGA and DSP.

Aiming at addressing the contradiction between the high-speed real-time positioning and multi-channel signal processing in multi-beam sonar systems, in this work we present a real-time multi-beam sonar system based on a Field Programmable Gate Array (FPGA) and Digital Signal Processing (DSP) from two perspectives, i.e., hardware implementation and software optimization. In terms of hardware, an efficient high-voltage pulse transmitting module and a multi-channel data acquisition module with time versus gain (TVG) compensation with characteristics such as low noise and high phase amplitude consistency, are proposed. In terms of algorithms, we study three beamforming methods, namely delay-and-sum (D&S), direct-method (DM) and Chirp Zeta Transform (CZT). We compare the computational efficiency of DM and CZT in the digital domain. In terms of software, according to the transmission bandwidth of the Gigabit Ethernet and a serial rapid IO (SRIO) interface, the data transmission paths of the acquired data and the beam pattern between the FPGA, the DSP, and a personal computer (PC) are planned. A master-slave multi-core pipelined signal processing architecture is designed based on DSP, which enhances the data throughput of the signal processor by seven times as compared with that of the single-core operation. The experimental results reveal that the sound source level of the transmitting module is around 190.25 dB, the transmitting beam width is 64° × 64°, the background noise of the acquisition module is less than 4 μVrms, the amplitude consistency error of each channel is less than −6.55 dB, and the phase consistency error is less than 0.2°. It is noteworthy that the beam number of the sonar system is 90 × 90, the scanning angle interval is 0.33°, the working distance ranges from 5 m to 40 m, and the maximum distance resolution is 0.384 m. In the positioning experiment performed in this work; the 3-D real-time position of the baffle placed in the detection sector is realized. Please note that the maximum deviation of azimuth is 2°, the maximum deviation of elevation is 2.3°, and the maximum distance deviation is 0.379 m.