Abstract
In synthesizing Digital signal processing (DSP) architecture, maintaining low silicon area and high performance becomes an important factor which can be achieved by various optimization techniques. To achieve this, we employ two design optimization techniques: folding and retiming, which are applied to 3rd order Chebyshev I high pass digital filter to minimize the functional units (adders, multipliers) and to reduce the number of registers. Folding transformation is used to determine the control circuits in DSP architecture by executing multiple algorithm operation on a single functional unit. Retiming using register minimization is applied after folding, thereby reducing the numbers of multipliers and adders from 7 to 1 and 6 to 1, respectively, without affecting the input and output characteristics of the filter. Key words: Data flow graph (DFG), Chebyshev filter, folding, retiming, lifetime analysis.
Highlights
INTRODUCTIONIts importance promotes advances in certain fields of applications such as telecommunication, military, instrumentation and control, image processing, seismology, speech processing and biomedical signal processing
Tremendous growth of digital signal processing (DSP)and its importance promotes advances in certain fields of applications such as telecommunication, military, instrumentation and control, image processing, seismology, speech processing and biomedical signal processing
Folding reduces the number of functional units; it may lead to the usage of large number of registers (Keshab, 2012; Rajalakshmi et al, 2013)
Summary
Its importance promotes advances in certain fields of applications such as telecommunication, military, instrumentation and control, image processing, seismology, speech processing and biomedical signal processing. DSP programs are executed repetitively for an infinite number of times and they are assumed to be non-terminating (Jackson et al, 2003; Salivahanan et al., 2010) This can be exploited by designing more efficient. To achieve the goals such as less area, high speed and low power different algorithms are proposed such as pipelining, folding, retiming etc. The transformation in which multiple algorithm operations are time multiplexed to a single functional unit is known as folding. This algorithm provides a technique for designing control circuits for hardware and helps to synthesize DSP architecture that can be operated using single or multiple clocks. This design optimization platform is designed using MATLAB/Simulink and Xilinx
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