Abstract
Digital Signal Processing (DSP) blocks are the backbone of all multimedia applications and Low Power is an imperative requirement for portable multimedia devices handling different signal processing algorithms and architectures. Human beings can capture useful information even if the output is having some error. Thus, we need not produce exact numerical outputs. Previous researches provide the error resiliency through Voltage Over Scaling (VOS) by various algorithms and architectures to reduce the errors. In this paper, the logic complexity reduction is proposed by using approximate adders which is obtained by reducing the number of transistors without reducing the quality of the output signal. Simulation results shows the power reduction by using approximate adders compared to the actual full adder cells.
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