Design of low power, area efficient and high speed approximate adders for inexact computing

Abstract

In most digital signal processing (DSP) applications like image processing and speech processing, human beings can collect useful information from slightly inexact outputs. This type of computing is referred as inexact computing which does not provide exactly correct numerical outputs. Inexact computing uses approximate circuits rather than exact circuits to perform the computations. Approximate circuits consume less power, require less number of transistors and have less propagation delay than exact circuits. Approximate adder is the building block of inexact computing for DSP applications. This paper presents a design of a 32-Bit approximate adder which has low power consumption and requires less number of transistors than existing approximate adders. The proposed approximate adder has power savings of 8% for 32-Bit as compared to existing designs. The proposed adder has significant reduction in area (number of transistors) than existing designs. All the circuits have been simulated in Cadence Virtuoso tool using 45-nm technology.