A Design of Low Power and Area efficient FIR Filter using Modified Carry save Accumulator Method

Abstract

In VLSI circuit designs, the reduction of power, area, and delay parameters are increasing as the range of sophistication of applications. Nowadays, there are many real-time applications needs low power with high throughput than never before getting the range. Here the FIR filter is used to design an efficient digital signal processing system. In FIR filter, the adders and multipliers are the important components to reduce the delay and area. Therefore, this proposed method faced with more constraints: high speed, high throughput, and at the same time, consumes as minimal power as possible. The Finite Impulse Response Filter is widely used in Digital Signal Processing Applications, such as speech processing, loudspeaker equalization, echo cancellation, noise cancellation, arithmetic computations and, image-processing applications. This work proposes a design of low power and area efficient Finite Impulse Response Filter using Modified Carry save adder. In FIR Filter design, the power determination is by the configuration, which selected by the ripples present in the execution of filter. The filtering process carried out by eliminating the ripples presented in the pass band and stop band of designed architecture. The FIR architecture is reframed by adders and multipliers used in the design. The proposed digital FIR filter design reduces the uses of adders and multiplier blocks for its efficiency in area and delay. Thus, the multipliers interchanged as adders for its area efficiency. The input data bits multiplied by a filter coefficient and then the ripple carry adder selects the particular adder cell to perform addition, which depends on carry input (Ci). This input bit performs at the last of carry save accumulation process. Similarly, next adder’s cell performs the same operations. The filtered output coefficient is getting from Carry save accumulation process. Thus, the proposed method can minimize the area, delay and power consumption of FIR filter design. Here with the use of Carry save adder with ripple carry adder gives the best optimization result. The Number of bonded inputs and outputs reduces the area of 24%. The experimental result achieves 24% of area reduction, 2% of delay and 3% of power consumption compared to the existing method. The Xilinx ISE 14.5 and Modelsim simulator is used to synthesis and simulation of the proposed architecture. The power consumption result analyzed by the Xilinx Power Estimator tool. This experimental result gives better robustness than most recent related literature.