VLSI implementation of residue number system based efficient digital signal processor architecture for wireless sensor nodes

Abstract

Residue number system (RNS) in computer arithmetic is an efficient parallel computation number system that employs forward conversion, residue arithmetic based arithmetic manipulation and reverses conversion, which all together increases the speed of computation in various digital signal processing applications. Nevertheless power requirement for the wireless sensor node is more important, hence this work focuses on the design and implementation of power efficient RNS based digital signal processor architecture using folded tree based parallel prefix adder by employing Chinese Remainder Theorem—I.