Abstract
An experimental evaluation of a digital control system based on a dual Digital Signal Processor (DSP) architecture is proposed for a three phase Unified Power Quality Conditioner (UPQC). A classical UQPC is constituted by two power conditioners, connected in series and shunted with the power grid, and sharing a common DC-link. In a smart grid scenario of operation, a UPQC will be fundamental for compensating power quality problems, also contributing to improving the efficiency of the electrical grids from a global perspective. The UPQC operation requires a bidirectional energy transfer between the two power conditioners, however, respecting some constraints, they can be controlled independently. In order to take advantage of this characteristic, the control algorithms can be executed on two independent DSPs, without any communication between them and maintaining the operational characteristics of the UPQC. Comparing with the classical control architecture based on a single DSP, with the proposed dual DSP architecture, the computational effort of each DSP is decreased of about 35%, allowing to increase the sampling rate. Therefore, the main advantages of the proposed approach are the minimization of delays caused by the processing time, which are very common in digital control systems, as well as the increment of the UPQC performance. Along the paper, detailed analysis of the processing speed and memory requirements to implement the UPQC control algorithms in both DSPs is presented. The paper also presents a set of detailed experimental results, obtained with a developed 5 kVA laboratory prototype of UPQC, which was used to evaluate the performance of the proposed dual DSP architecture.
Highlights
The Unified Power Quality Conditioner (UPQC) is a custom power device integrating two conditioners in a back-to-back configuration and presenting series and shunt connections to the power grid [1]
The control algorithms based on the active- and non-active currents have been chosen, since they are simple to be implemented in a Digital Signal Processor (DSP), with the shunt conditioner able to improve most of the power quality indices at the point where it is connected to the power grid
A dual-DSP control architecture for a three-phase Unified Power Quality Conditioner (UPQC) is proposed in this paper, and a set of experimental results based on two test cases are presented and discussed
Summary
The Unified Power Quality Conditioner (UPQC) is a custom power device integrating two conditioners in a back-to-back configuration and presenting series and shunt connections to the power grid [1]. It must be referred that even with the increment in the number of the power switches, this topology was the most applied in similar conditions where the UPQC without series transformers, was connected in low and medium voltages power grids. In the scope of this paper, two DSPs, model TMS320F2812 from Texas Instruments, were used to implement all of the UPQC control algorithms, including the PWM outputs to drive the power switches These DSPs were selected considering that they are low-cost processors with internal RAM, flash ROM memory, ADCs, timers, PWM and other peripherals which make them suitable for rapid prototyping and a considerable amount of applications as, for example, real-time control of power electronics [18,19].
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