Signal Integrity Performance Research Articles

XGBoost-enabled low-complexity approach for signal integrity assessment in coherent communication systems

Abstract Error vector magnitude (EVM) provides critical information for assessing signal integrity and system performance in optical communication systems. In this research, a regression approach using boosting algorithms is developed to retrieve EVM information from complex signal constellation structures applicable to various modulation formats. Amplitude histograms are created and collected at different OSNR levels, launch powers, and transmission distances using an offline preprocessing approach. The impact of various evaluation techniques, including mean absolute error, coefficient of determination, root mean square error (RMSE), and mean absolute percentage error (MAPE) is discussed in detail. The results show that the proposed extreme gradient boosting framework considerably increases estimation precision compared to categorical boosting and light gradient boosting machine, especially under diverse transmission conditions, with MAPE staying below 1.7% and RMSE below 0.5, thereby enhancing overall performance monitoring in optical communication systems. This research provides a comprehensive and accurate representation of the proposed EVM estimation technique, making it a valuable resource for the development of advanced optical performance monitoring systems in the future.

Multi-physical field coupling effect in micro pin-fin channel cooling with coaxial-like through-silicon via (TSV) for three-dimensional integrated chip (3D-IC)

Through-silicon via (TSV) technology offers significant advantages for three-dimensional integrated chip (3D-IC) by enabling higher integration densities and faster signal transmission rates. The increased power density of 3D-IC poses substantial thermal management challenges. Microchannel cooling is widely used for chip-level thermal management. However, the balance of heat dissipation and signal integrity between layers of 3D-IC with TSV remains elusive. This work presents a study on the electrical-thermal-force-flow-solid multi-physics field coupling effect of micro pin–fin channel cooling systems embedded with coaxial-like TSVs in 3D-IC, aiming to optimize signal integrity and thermal performance. We analyze the structural parameters of coaxial-like TSVs, such as TSV aspect ratio and pitch ratio, focusing on their impact on signal shielding efficiency and thermal conductivity. The results show that a coaxial-like TSV structure with an aspect ratio of 15 and a pitch ratio of 2.5 reduces the maximum temperature and insertion loss by 3.97% and 3.60%, respectively. This structure is then embedded in a micro pin–fin channel to explore the effect of pin–fin arrangement on heat dissipation at different Reynolds numbers. Using multi-objective optimization through response surface methodology (RSM) and the non-dominated sorting genetic algorithm II (NSGA-II), we obtain a series of optimal solutions for TSV-embedded micro pin–fin. When the weights of heat transfer and pressure drop are balanced, the average Nusselt number increases by 6.8% with a 2% rise in pressure drop. These findings provide valuable insights for the design and optimization of high-performance 3D-IC cooling systems.

IQ-channel multiplexed DP-4ASK signal using power loading for downlink coherent PON system with access-span length difference

This study explores the integration of dual-polarized (DP) four-level amplitude shift keying (4ASK) signals within an intensity and quadrature division multiplexing framework, mainly focusing on coherent passive optical network (PON) systems. The primary objective is to address the challenges associated with distance disparities in downstream transmissions, which are prevalent in coherent PON architectures. We introduce a novel approach that significantly reduces the power consumption of digital-to-analog converters by implementing power loading strategies tailored explicitly for IQ channel division multiplexing (IQDM)-DP-4ASK signals. Our simulations confirm that ASK standard frequency offset compensation is adaptable to these signals, providing a robust method for managing frequency offsets in a dynamic network environment. Moreover, we propose and empirically validate an energy-efficient adaptive downlink solution capable of supporting 128 Gb/s per optical network unit (ONU), utilizing IQ-imbalanced DP-4ASK signals. This solution is particularly advantageous for systems where the transmission conditions include a 10 km variance in access span lengths between ONUs. Results from our experimental setup demonstrate that reducing the digital-to-analog converter output current for the Q channel by 137 mA is feasible without compromising signal integrity or system performance. Additionally, the research verifies the effectiveness of the automatic bias controller on the transmitter side, ensuring stable operation across varying conditions. Equally, the receiver-side digital signal processing effectively handles polarization separation, illustrating the system's capability to maintain high data integrity and reliability under diverse operational scenarios. These findings highlight the technical feasibility and operational benefits of using IQDM-DP-4ASK signals in coherent PON systems and underscore the potential for significant power savings and enhanced system efficiency in optical networks. The study paves the way for future research into scalable, energy-efficient solutions suitable for high-capacity optical access networks striving for increased sustainability and reduced operational costs.

A full-function Global Common Module prototype for ATLAS Phase-II upgrade

The High Luminosity Large Hadron Collider (HL-LHC [1]), an upgrade of the LHC, is set to become operational in 2029, aiming to achieve instantaneous luminosities 5–7.5 times larger than the nominal value of the LHC. However, unlocking the full physics potential at this much higher luminosity level necessitates a tenfold increase in the data bandwidth processed by ATLAS. This poses significant challenges to the design of the Trigger and Data Acquisition systems. To address these challenges, a baseline architecture has been chosen for the ATLAS Phase-II upgrade, relying on a single-level hardware trigger known as the Level-0 Trigger. This trigger has a maximum rate of 1 MHz and a latency of 10 μs. Central to this upgrade is the inclusion of a new subsystem — the Global Trigger [2]. This component performs complex algorithms, akin to those currently used in Phase-I high-level trigger software (such as Topoclustering), on full-granularity calorimeter data. The Global Trigger is divided into three sublayers: the Multiplexer Processor (MUX) layer, the Global Event Processor (GEP) layer, and the Global to Central Trigger Processor [3] interface (gCTPi). A full-function Global Common Module (GCM) hardware prototype has been designed to fulfill the requirements of all three sublayers of the Global Trigger, featuring different firmware loads. This GCM prototype, based on the ATCA [4] front board form factor, incorporates two of the latest AMD (Xilinx) Versal Premium devices VP1802 [5]. These devices boast double the density of the Virtex UltraScale+ FPGA VU13P used in the previous design [6] and include an integrated SoC with a completely new architecture. To handle high-speed I/Os, this GCM prototype employs twenty 12-channel 25.7 Gb/s FireFly [7] optical engines. The estimated maximum power consumption of this GCM prototype is 400 W, which falls within the cooling capabilities of the ATLAS ATCA shelf. To ensure power integrity, signal integrity, and thermal performance, extensive PCB simulations and thermal simulations have been done to guide the layout design of the GCM prototype. This paper provides an in-depth overview of the design process for this full-function GCM prototype hardware, with a particular focus on technology choices and simulation results.

S‐parameter extraction for electromagnetic modelling of memristor‐based crossbar array circuits

AbstractThis article presents an efficient S‐parameter extraction method for memristor‐based crossbar array circuits. The proposed approach involves converting the array into an equivalent circuit and analytically solving the circuit to obtain the S‐parameters. Memristor‐based crossbar array circuit simulations and corresponding experimental measurements are conducted to verify the high accuracy and low computation complexity of the established method. These numerical results indicate that the authors’ S‐parameter extraction method has the potential for evaluating signal integrity performance in neuromorphic chips, thus aiding their design and optimization for diverse applications.

Low Loss/Low CTE Semiconductor Carrier Packaging Thin Core Material

There is an ever-increasing need by semiconductor/packaging companies for the introduction of a low loss, ultra-low Coefficient of Thermal Expansion chip carrier packaging substrate core material that provides a cost-effective method for producing thin core build up with very dense core vias. This low loss, low CTE flip-chip substrate core is well suited to multi-layer, RF, and applications requiring a system-in-package approach. This paper discusses a novel substrate core material using a build-up film dielectric layer in conjunction with glass fiber weave. Key properties include low loss (Df<0.002), a CTE from 5 - 10 ppm/C, extremely high thermal reliability, and low modulus. An advantage of using glass fiber weave instead of Invar, for instance, is the extremely low CTE that can be achieved while still maintaining a non-conductive power or ground plane. Multilayer circuits using PTFE can suffer from extremely high lamination temperatures, high cost, and low overall yields due to the inability of the soft material to go through a desmear process. Substrate core materials have the primary benefit that they offer stability and increased reliability of many subsequent build-up microvia layers. As monolithic semiconductors are replaced by chiplets, there is a growing need to package many types of chiplets without losing the signal integrity performance of a monolithic semiconductor on a single IC package. An extremely low loss substrate core offers the potential benefit that unique chiplet packaging architectures can be designed with the lowest possible dielectric losses due to the multichip interconnect strategy.

Inhomogeneous Dielectric Induced Skew Modeling of Twinax Cables

To understand the skew in twinax cables of separately extrusion and co-extrusion design, the impact of inhomogeneous dielectric in copper twinax cables is analyzed, with an emphasis on signal integrity performance. The inhomogeneity is treated as a perturbation to the RLGC parameters, and analytical equations for calculation of scattering parameters from RLGC parameters are derived to analyze the effects of this perturbation on signal integrity. The inhomogeneity leads to a modulation behavior in the scattering parameters, which decreases asymmetry induced skew at high frequencies and eliminates the resonance of skew in the differential insertion loss. Mathematical analysis, the physical explanation, and various design cases are presented for validation.

A three-dimension terminal simulation tool based on transfinite element method

In the design of high-speed interconnection systems, it is often necessary to evaluate signal integrity and electromagnetic interference performance by extracting terminal network parameters and differential and common mode network parameters. However, in a multi-conductor transmission line, the characteristic parameters related to different conductors, which named terminal in terminal theory, are couped together in traditional model network parameters and could not be extracted directly. Therefore, in this paper, a three-dimension terminal simulation tool based on transfinite element method is developed to solve this problem. The vector finite element method is combined with the transfinite element method, and the electric field of the truncation surface is approximated by the expansion of the truncation surface mode function. As far as we know, the combination of the transfinite element method and the terminal theory is proposed for the first time. The terminal simulation tool has a human-computer interaction interface, as well as functions such as modeling, mesh generation, solution setting, and post-processing result display, which can accurately obtain the terminal network parameters and differential and common mode network parameters. Numerical examples are given to demonstrate the accuracy and efficiency of the developed tool compared with the results from HFSS.

Multiobjective Optimization for Heat Transfer Performance of Micro-Fins and Signal Integrity of Key Interconnect Technologies in 3-D Integrated Chips

This article is devoted to the synergistic design of the thermal management and signal integrity for 3-D integrated chips. The structure parameters of the micro-fin and interconnected components are optimized to obtain a balanced performance of chip heat dissipation and signal integrity. The 3-D integrated chip flows heat transfer model under the action of electrothermal coupling is developed. A full-wave electromagnetic simulation model of the signal interconnection components is proposed with the same structural parameters. The effects of various structural factors on the heat transfer performance and signal integrity of 3-D integrated chips are investigated. A multiobjective optimization algorithm is carried out to simultaneously reduce the total thermal resistance of the 3-D integrated chip and the signal transmission losses of the critical interconnect components. The results show that the total thermal resistance of the 3-D IC becomes lower with a larger through-silicon via (TSV) diameter, micro-fins height and micro-fin radius, and smaller oxide thickness. When the TSV diameter and oxide thickness increase, the height and radius of the micro-fins are reduced to facilitate the signal transmission of the chip’s interconnected components. The response surface analysis method was used to design the experimental combination and thus obtain the fit function for the performance of the two objectives. Hundred sets of Pareto optimal solutions are obtained by multiobjective optimization. The technique for order preference by similarity to ideal solution (TOPSIS) method is used to select the weights of the two optimization objectives to determine the optimal solution. When thermal resistance and signal transmission are given equal weight in the chip design, thermal resistance is reduced by 13.8%, and signal transmission efficiency is improved by 9.74%. The study has important implications for chip thermal management and signal integrity.

분할 공동 구조를 이용한 고 종횡비 인쇄회로기판 내 전송선 층 변환 구조의 신호 무결성 개선 설계 및 모델링

This paper proposed a layer transition design for high-speed signal transmission in high aspect ratio printed circuit boards (PCBs). The proposed design employed a segmented cavity structure to suppress the group cavity resonance that degrades a wide bandwidth range of high-speed transmission lines with signal vias for layer transition. To predict the transfer characteristic of the proposed design, equivalent circuit models were developed based on the combination of resonant cavity models, lumped via models, and conventional transmission line models. The proposed design and equivalent circuit models were validated with a noticeable improvement in the signal integrity performance by simulation and measurement results up to 30 GHz.

SI Considerations in Flexible Channels on High-Speed Intra-Panel Interface for Large-Size Flat Panel Display Applications

In flat panel display modules with a large-size and high-resolution for TV applications, signaling channels are relatively short on flexible printed circuit (FPC) cable or chip-on-film (COF) package when compared to those of the source PCBs. However, the short distance channels can significantly affect overall signal integrity (SI) performance. Thus, this letter focuses mainly on analysis and design of signal interconnection on FPC cable and COF package in terms of impedance matching and crosstalk. By optimizing the FPC cable design to mitigate crosstalk as well as insertion loss, the opening area of eye diagram was found to be improved more than twice over the previous one. In addition, through adjusting process of on-die capacitance of electro-static discharge (ESD) protection circuitry in the input stage of a high-speed circuit block, the created parasitic inductance of COF package trace was observed to be compensated. This optimization process can improve greatly system performance by widening the input eye opening. Finally, we propose channel design considerations and design guidelines to ensure better SI performance in flexible channels on high-speed intra-panel interface for large-size liquid crystal display (LCD) TV applications.

Prepreg and Core Dielectric Permittivity (ϵr ) Extraction for Fabricated Striplines’ Far-End Crosstalk Modeling

As the data rate and density of digital high-speed systems are getting higher, far-end crosstalk (FEXT) noise becomes one of the major issues that limit signal integrity performance. It was commonly believed that FEXT would be eliminated for striplines routed in a homogeneous dielectric, but in reality, FEXT can always be measured in striplines on the fabricated printed circuit boards. A slightly different dielectric permittivity (<inline-formula><tex-math notation="LaTeX">${{\boldsymbol{\varepsilon }}_{\boldsymbol{r}}}$</tex-math></inline-formula>) of prepreg and core may be one of the major contributors to the FEXT. This article is focusing on providing a practical FEXT modeling methodology for striplines by introducing an approach to extract <inline-formula><tex-math notation="LaTeX">${{\boldsymbol{\varepsilon }}_{\boldsymbol{r}}}$</tex-math></inline-formula> of prepreg and core. Using the known cross-sectional geometry and measured <i>S</i>-parameters of the coupled stripline, the capacitance components in prepreg and core are separated using a two-dimensional solver, and the <inline-formula><tex-math notation="LaTeX">${{\boldsymbol{\varepsilon }}_{\boldsymbol{r}}}$</tex-math></inline-formula> of prepreg and core is determined. A more comprehensive FEXT modeling approach is proposed by applying extracted inhomogeneous dielectric material information.

Reinforcement-Learning-Based Signal Integrity Optimization and Analysis of a Scalable 3-D X-Point Array Structure

In this article, we, for the first time, propose a reinforcement learning (RL) model to design an optimal 3-D cross-point (X-Point) array structure considering signal integrity issues. The interconnection design problem is modeled to the Markov decision process (MDP). The proposed RL model designs the 3-D X-Point array structure based on three reward factors: the number of bits, the crosstalk, and the IR drop. We applied multilayer perceptron (MLP) and long short-term memory (LSTM) to parameterize the policy. Proximal policy optimization (PPO) is used to optimize the parameters to train the policy. The reward of the proposed RL model is well-converged with variations in the array structure size and hyperparameters of the reward factors. We verified the scalability and sensitivity of the proposed RL model. With the optimal 3-D X-Point array structure design, we analyzed the reward factor and signal integrity issues. The optimal design of the 3-D X-Point array structure shows 17&#x0025;&#x2013;26.5&#x0025; better signal integrity performance than the conventional design in finer process technology. In addition, we suggest a range of possible directions for improvement of the proposed model with variations in MDP tuples, reward factors, and learning algorithms, among other factors. Using the proposed model, we can easily design an optimal 3-D X-Point array structure with a certain size, performance capabilities, and specifications based on reward factors and hyperparameters.

Multi-Objective Optimization for Heat Transfer Performance of Micro-Fins and Signal Integrity of Key Interconnect Technologies in 3d Integrated Chips

Multi-Objective Optimization for Heat Transfer Performance of Micro-Fins and Signal Integrity of Key Interconnect Technologies in 3d Integrated Chips

Far-End Crosstalk Modeling and Prediction for Stripline With Inhomogeneous Dielectric Layers (IDLs)

Far-end crosstalk (FEXT) is a critical factor that limits signal integrity performance in high-speed systems. The FEXT level is sensitive to the dielectric inhomogeneity of the stripline in fabricated printed circuit boards (PCB). The dielectric of the stripline is manufactured with multiple inhomogeneous dielectric layers (IDLs) of various resin and glass fiber bundles. A marginal difference in the dielectric permittivity of the IDLs can lead to a significant change FEXT level. In this paper, a practical FEXT modeling methodology for striplines is proposed by introducing the extraction method for the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${{\bm{\varepsilon }}}_{\bm{r}}$</tex-math></inline-formula> of IDLs. The new stripline model is constructed with three IDLs comprised of core, prepreg, and resin pocket, to improve the model accuracy. With the cross-sectional geometry and measured S-parameters of the coupled striplines, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${\bm{\ }}{{\bm{\varepsilon }}}_{\bm{r}}$</tex-math></inline-formula> of IDLs can be extracted. In addition, an analytical model to predict the FEXT polarity and magnitude of the stripline caused by the inhomogeneity is proposed targeted for pre-layout application. The proposed models have been verified using measurement. The proposed models can provide useful analysis methodology and design guidelines to mitigate the FEXT level in high-speed systems, especially for high-volume PCB tests in the pre-layout and post-layout stages.

Practical Papers, Articles and Application Notes

Low temperature cofired ceramics (LTCC) are a popular choice for integration of both high-frequency electronics and passive components in a compact package. Just like any other electronic packaging technology, vias are widely used in LTCC for signal routing as well as power delivery within the layered stack-up. It is well known that vias introduce discontinuities in the signal and power delivery paths and can degrade the signal and power integrity performance. The first paper, “Introducing Functional Via Structures to Low Temperature Cofired Ceramics: How to Optimize Reliably and Efficiently”, intends to develop efficient ways to estimate and control via impedance and phase delay. It adopts the concept of functional via structures that is based on the generalization of vias as quasi-coaxial lines that behave like transmission lines. Based on the concept of functional via structures, via impedance and phase delay can be optimized for LTCC multilayered substrates up to 40 GHz for most practical applications.

Study on Power Integrity and Signal Integrity Issues

High frequency channel loss, reflection, and crosstalk are causing degradation of the receiver eye opening, jitter performance, and bit error rate. The voltage drop and current density wisely affects the performance of the PCB.The increase in current density in turn increases the temperature of the board which might cause fault in performance or even explosion of the device. In addition, improper PCB design can lead to noncompliance with EMC regulations. The physical design changes required to meet the use case conditions negatively impact the signal and power integrity performance, limiting the speeds and capabilities that are achievable. The signal and power integrity desires directly oppose one another, so a holistic platform design approach is required to optimize system performance. Since power integrity affects the entire device, from the chip to the chip package to the board to the entire system, a variety of factors must be considered to ensure the design.

Impact of receptacle degradation and loose connection on signal integrity and electrical performance repeatability

Radio frequency (RF) coaxial connectors are important constituents of modern communication systems. The degraded electrical contacts may adversely affect the signal transmission efficiency particularly in the case of loose connections. In this study, a distributed equivalent model of a coaxial connector with degraded receptacle and the loose connection was developed. The scattering parameters were analysed from the perspectives of both experimental testing and model simulation. The equivalent model and experimental results show good agreement. The impact of the degraded receptacle and loose connection on signal integrity was studied along with its electrical performance repeatability for different cases with respect to a degraded and loose connector. In addition, for the same degradation and loose level, the variation of contact resistance and contact capacitance was also investigated. These results are helpful for a better understanding of the intermittent failure of RF connectors. Moreover, these conclusions are also useful for diagnosing circuit faults caused by deteriorated repeatability of degraded and loose connectors.

CST Analysis and Simulation of Signal Integrity of Differential Transmission Lines

The differential transmission line has been widely used in the field of high-speed signals with its unique transmission characteristics, and it will be affected by many factors during the transmission process. In this paper, the differential transmission line is taken as the research object, and a three-dimensional electromagnetic simulation software CST is used to study its signal integrity performance parameters including characteristic impedance, loss, and crosstalk. It is found through simulation that increasing the spacing between differential pairs will reduce the crosstalk. The smaller the differential pair length, the greater the value of the insertion loss. This will improve the quality of signal transmission.

A Temperature and Dielectric Roughness-Aware Matrix Rational Approximation Model for the Reliability Assessment of Copper– Graphene Hybrid On-Chip Interconnects

In this article, a closed-form matrix rational approximation (MRA) model is presented for the reliability assessment of copper–graphene hybrid on-chip interconnect networks. The key feature of this MRA model is its capacity to predict how the different values of temperature and dielectric roughness affect the signal integrity performance of the hybrid interconnect networks. As a result, the proposed MRA model is well suited for very fast parametric sweeps and worst case analysis of the hybrid interconnect networks, which has not been possible using existing closed-form models or even SPICE simulations. Numerical examples show that the proposed model is significantly more efficient than conventional models while exhibiting error less than 5%.