Low Loss/Low CTE Semiconductor Carrier Packaging Thin Core Material

Abstract

There is an ever-increasing need by semiconductor/packaging companies for the introduction of a low loss, ultra-low Coefficient of Thermal Expansion chip carrier packaging substrate core material that provides a cost-effective method for producing thin core build up with very dense core vias. This low loss, low CTE flip-chip substrate core is well suited to multi-layer, RF, and applications requiring a system-in-package approach. This paper discusses a novel substrate core material using a build-up film dielectric layer in conjunction with glass fiber weave. Key properties include low loss (Df<0.002), a CTE from 5 - 10 ppm/C, extremely high thermal reliability, and low modulus. An advantage of using glass fiber weave instead of Invar, for instance, is the extremely low CTE that can be achieved while still maintaining a non-conductive power or ground plane. Multilayer circuits using PTFE can suffer from extremely high lamination temperatures, high cost, and low overall yields due to the inability of the soft material to go through a desmear process. Substrate core materials have the primary benefit that they offer stability and increased reliability of many subsequent build-up microvia layers. As monolithic semiconductors are replaced by chiplets, there is a growing need to package many types of chiplets without losing the signal integrity performance of a monolithic semiconductor on a single IC package. An extremely low loss substrate core offers the potential benefit that unique chiplet packaging architectures can be designed with the lowest possible dielectric losses due to the multichip interconnect strategy.