Self-aligned Electrodes Research Articles

A Reduced Mask-Count Technology for Complementary Polycrystalline Silicon Thin-Film Transistors With Self-Aligned Metal Electrodes

The inexpensive glass substrate for building conventional low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) imposes a ceiling on the TFT processing temperature. This results in a reduced efficiency of dopant activation and a high source/drain series resistance. A technique based on aluminum-induced crystallization of amorphous silicon has been applied to fabricate TFTs with low-resistance self-aligned metal electrodes (SAMEs). While at least two masked implantation steps are typically used for constructing the doped source and drain regions of conventional n- and p-channel TFTs in a complementary metal-oxide-semiconductor circuit technology, it is currently demonstrated that complementary SAME poly-Si TFTs can be constructed using a combination of a masked and a blanket source and drain implantation steps. The decrease in mask count reduces process complexity and cost. Control of ion channeling is the enabling factor behind the successful demonstration of the technology.

A Polycrystalline Silicon Thin-Film Transistor With Self-Aligned Metal Electrodes Formed Using Aluminum-Induced Crystallization

A low-temperature technology for the fabrication of a polycrystalline silicon (poly-Si) thin-film transistor (TFT) with self-aligned metal electrodes (SAMEs) is demonstrated. The conventional poly-Si source and drain regions are amorphized by self-aligned dopant implantation before they are replaced by aluminum via an aluminum-induced crystallization (AIC) process. AIC is selective between amorphous and poly-Si. No deliberate dopant activation process is needed, and the field-effect polarity of a SAME poly-Si TFT is determined by that of the dopant used for the amorphization. SAME poly-Si TFTs with channel lengths down to 1 have been realized. The effects of aluminum thickness on AIC and those of the AIC annealing temperature and time on the performance of a SAME poly-Si TFT are also reported.

Tunneling spectroscopy of a germanium quantum dot in single-hole transistors withself-aligned electrodes

We have fabricated a Ge quantum dot (QD)(∼10 nm) single-hole transistor with self-aligned electrodes using thermal oxidationof a SiGe-on-insulator nanowire based on FinFET technology. This fabricateddevice exhibits clear Coulomb blockade oscillations with large peak-to-valleyratio (PVCR) of 250–750 and negative differential conductance with PVCR of∼12 at room temperature. This reveals that the gate-induced tunneling barrier lowering iseffectively suppressed due to the self-aligned electrode structure. The magnitude oftunneling current spectra also reveals the coupling strengths between the energy levels ofthe Ge QD and electrodes.

High performance ZnO nanowire field effect transistor using self-aligned nanogap gate electrodes

A field effect transistor (FET) using a zinc oxide nanowire with significantly enhanced performance is demonstrated. The device consists of single nanowire and self-aligned gate electrodes with well defined nanosize gaps separating them from the suspended nanowire. The fabricated FET exhibits excellent performance with a transconductance of 3.06μS, a field effect mobility of 928cm2∕Vs, and an on/off current ratio of 106. The electrical characteristics are the best obtained to date for a ZnO transistor. The FET has a n-type channel and operates in enhancement mode. The results are close to those reported previously for p-type carbon nanotube (CNT) FETs. This raises the possibility of using ZnO as the n-type FET with a CNT as the p-type FET in nanoscale complementary logic circuits.

Ultracompact electron-beam column

An electron optical system with an array of columns was developed for an electron-beam addressable data storage device that has the form factor of Compact Flash and a capacity >10GB. The electron optical column occupies an area <2500μm2 and produces a focused beam with current <100nA and a diameter <40nm. An extended-area electron source that consists of an array of randomly distributed hemispherical-grain polysilicon nodules was developed. The field at the nodules is enhanced by a factor of 3–5 compared with metal-insulator-semiconductor structures with smooth cathodes. Electron emission consequently occurs predominantly at the nodules. A maximum current density of ∼20A∕cm2 was achieved with this electron source. The multiplicity of emission sites helps us to reduce significantly the emission current noise. An electron optical column to focus the emission from this extended source into a diameter <30nm was also developed. The column consists of a single main lens and an array of auxiliary nanolenses. The main lens has a diameter of ∼3μm. The distance between the main lens and the electron source is ∼3μm. Each electron emission nodule has a self-aligned extraction electrode and a nanolens whose diameters are ∼0.03–0.1μm. The nanolenses collimate the electron emission from the nodules. The main lens then focuses the collimated beams into a diameter of ∼30nm at an image distance of ∼3μm. Without the nanolenses, the main lens alone can only focus the beam into a diameter of ∼300nm.

High Performance pMOSFETs with High Ge Fraction Strained SiGe-heterostructure-channel and Ultrashallow Source/Drain Formed by Selective B-Doped SiGe CVD

The improvement of current drivability and short channel effect is very important for ultrasmall MOS devices technology. SiGe-channel pMOSFETs are one of the most promising devices because hole mobility in the SiGe layers is enhanced. In the previous work, it has been reported that Super self-aligned shallow junction electrode (S3E) MOSFETs formed by selective B-doped SiGe CVD are effective for the suppression of short channel effect. In this paper, it is clarified that the (S3E) pMOSFETs with Si0.65Ge0.35-channel are realized not only with suppression of punch through due to the ultrashallow B-diffused source/drain but also with enhancement of maximum linear transconductance due to the low parasitic resistance, compared to that with the Si-channel fabricated by the same process conditions.

Fabrication of a nanoelectromechanical switch using a suspended carbon nanotube

Fabrication and characterization of a nanoelectromechanical switching device consisting of a suspended multiwalled carbon nanotube and self-aligned electrodes is reported. The device has a triode structure and is designed so that a suspended carbon nanotube is mechanically switched to one of two self-aligned electrodes by repulsive electrostatic forces between the nanotube and the other self-aligned electrode. Carbon nanotubes are dispersed on an SiO2 coated Si wafer and their locations recorded using a scanning electron microscope mapping process. Contact electrodes and self-aligned deflection electrodes are formed by a process comprising electron beam lithography, metallic thin film deposition, and lift-off. The electrical measurements show well-defined ON and OFF states with change of gate voltage. The measured threshold voltage for electromechanical switching is ∼3.6V.

Reduced Hot Carrier Effects in Self-Aligned Ground-Plane FDSOI MOSFET’s

This paper reports the hot-carrier induced device degradation of fully depleted (FD) n-channel SOI MOSFETs with a self-aligned ground-plane electrode in the silicon substrate underneath the buried oxide. The ground-plane configuration is shown to reduce short-channel effects, BJT effects and hot-carrier effects. Based on measurements of hot-carrier degradation rate, it is predicted that the maximum allowable supply voltage of ground-plane FDSOI MOSFET is higher than that of FDSOI device without a ground plane.

Carbon nanotubes field emission devices grown by thermal CVD with palladium as catalysts

The effects of palladium (Pd) catalyst film thickness and ammonia (NH 3) in thermal chemical vapor deposition (CVD) growth of carbon nanotubes (CNTs) are systematically compared per the resulting morphologies, Raman spectra and field emission characteristics. The CNT field emitters were tested under identical experimental configurations. Field emission characteristics were described with Fowler-Nordheim field emission theory. Experimental results demonstrate that thermally grown CVD CNTs configured as diode field emitters exhibit low turn-on fields and high emission current density. The work is extended to include the study of gated field emitters or field emission triode, important to achieving high-resolution, full gray-scale imaging for field emission, flat-panel displays. The gated device was fabricated utilizing single-mask, self-aligned gate electrode with conventional integrated-circuit (IC) fabrication process. The CNT-triode showed gate-controlled modulation of emission current where higher gate voltage gives rise to higher anode currents. The triode fabrication process using silicon-on-insulator (SOI) wafers is discussed.

Sub-micron structuring at mesa edges

A simple process for forming sub-micron gaps between horizontal and vertical electrodes in a three-dimensional micro-electrode system without the need for high-resolution lithography is described. The process is based on the enhancement of ion milling rates in metals at oblique ion incidence, which allows the preferential erosion of metal at a mesa edge. Self-aligned electrode structures are formed on silica and oxidised silicon mesas, and electrode separations of 150–300 nm are demonstrated in geometries that may be suitable for vertical knife-edge field emission sources.

Sub-micron structuring at mesa edges

A simple process for forming sub-micron gaps between horizontal and vertical electrodes in a three-dimensional micro-electrode system without the need for high-resolution lithography is described. The process is based on the enhancement of ion milling rates in metals at oblique ion incidence, which allows the preferential erosion of metal at a mesa edge. Self-aligned electrode structures are formed on silica and oxidised silicon mesas, and electrode separations of 150–300 nm are demonstrated in geometries that may be suitable for vertical knife-edge field emission sources.

Fabrication of 0.12 μm pMOSFETs on high Ge fraction Si/Si 1− xGe x/Si(1 0 0) heterostructure with ultrashallow source/drain formed using B-doped SiGe CVD

High Ge fraction Si/Si 1− x Ge x /Si heterostructures ( x=0.5) are processed into the super self-aligned ultrashallow junction electrode (S 3E) pMOSFETs. The ultrashallow junction is made from the selective epitaxial B-doped Si 0.5Ge 0.5 on source/drain grown by chemical vapor deposition (CVD) and subsequent thermal diffusion of B from B-Si 0.5Ge 0.5 into the substrate. The Ge fraction in the S 3EMOSFETs’ buried layer changes to 0.35 after the B diffusion at 750 °C due to the interdiffusion between Si and Ge. The B diffusion depth in Si/SiGe/Si is shallower compared to that in Si. Compared to Si-channel S 3EMOSFET, the maximum linear transconductance of the 0.12 μm gate Si 0.65Ge 0.35-channel S 3EMOSFET increases by approximately 45%. The threshold voltage shift and the S factor degradation in the short channel region are well suppressed compared to the Si-channel S 3EMOSFETs. It is suggested that the suppression of short channel effects is caused by the ultrashallow source/drain and the valence band discontinuity at the Si 1− x Ge x /buffer Si interface.

Micro-tip array fabrication by selective anodization of p-type Si substrate

Crystal Si micro-tip arrays were fabricated by selective anodization of p + -type Si substrate using an n-type doped layer as mask. The use of p + -type substrate gave rise to sideway anodization with a moderate degree of current restriction patterning effect under the n-type mask layer, and triggered the formation of a sharp tip on the Si substrate. A process that allows for the fabrication of tip arrays with a self-aligned gate electrode was also studied. In the latter process, anodization through a donut-shape window within the n-type doped area prompted the formation of a tip with surrounding Si wall with the top n-type layer as a gate.

Self-aligned electrodes for suspended carbon nanotube structures

We report on a study into electrode fabrication for the gate control of carbon nanotubes partially suspended above an oxidised silicon substrate. A fabrication technique has been developed that allows self-aligned side-gate electrodes to be placed with respect to an individual nanotube with a spacing of less than 10 nm. The suspended multi-walled carbon nanotube (MWCNT) is used as an evaporation mask during metal deposition. The metal forms an island on the nanotube, with increasing width as the metal is deposited, forming a wedge shape, so that even thick deposited layers yield islands that remain separated from the metal deposited on the substrate due to shadowing of the evaporation. The island can be removed during lift-off to leave a set of self-aligned electrodes on the substrate. Results show that Cr yields self-aligned side gates with around 90% effectiveness.

TM-pass polymer modulators with poling-induced waveguides and self-aligned electrodes

Transverse magnetic (TM) mode selective polymer Mach-Zehnder modulators with self-aligned electrodes were fabricated for the first time in the electro-optic polymer material APC-CPW1 by employing a poling-induced (PI) writing method. The waveguides support only a TM polarisation, when an arbitrarily polarised optical source is incident. Modulators with a single 3 cm long driving electrode show a V/sub /spl pi// of 3.5 V at 1.55 /spl mu/m.

Fabrication of Ferroelectric Microcapacitors with Self-Aligned Top Electrodes by Electron-Beam-Induced Patterning Process

Ferroelectric Pb(Zr,Ti)O3 (PZT) microcapacitors were fabricated by the modified electron-beam-induced patterning process which we proposed. Electron beam irradiation decreased the thickness of precursor films and made them insoluble in organic solvent. Platinum thin films were deposited on the precursor films with hollows generated by electron beam irradiation. The acceleration voltage of an electron beam was decreased from 25 to 10 kV in order to form suitable hollows for lift-off. It seems that the scattered electron beam generated sidewalls with a reversed tapered shape. Only the Pt thin films on the unirradiated area were removed with precursor films by development, and self-aligned top electrodes were formed on the top of the remaining ferroelectric micropatterns using the lift-off technique. The 800 ×800 nm2 PZT microcapacitors were successfully fabricated by this process. The PZT capacitors with sizes larger than 3 ×3 µm2 exhibited ferroelectric properties, although remanent polarization was lower than that of PZT thin films fabricated by the conventional chemical solution deposition technique.

Super self-aligned technology of ultra-shallow junction in MOSFETs using selective Si 1− xGe x CVD

The fabrication process is investigated to improve the super self-aligned ultra-shallow junction electrode MOSFET (S 3EMOSFET) by utilizing in-situ impurity-doped Si 1− x Ge x selective epitaxy on the source/drain regions at 550 °C by means of LPCVD. It is found that phosphorus-doped Si 1− x Ge x films with a high Ge fraction have low solid solubility of electrically active phosphorus, and boron-doped Si 1− x Ge x films with a high Ge fraction have a low barrier height for tungsten. Therefore, both a Si 1− x Ge x film with a low Ge fraction and one with a high Ge fraction are necessary to fabricate n- and p-MOSFETs with low contact resistivity. A super self-aligned process on the source/drain regions using selective in-situ-doped Si 1− x Ge x growth, shallow junction formation, and subsequent very-low-temperature tungsten growth are effective in reducing the source/drain resistance. 0.1 μm gate pMOSFETs are fabricated by means of the super self-aligned technology. They show good drain current drivability and roll-off characteristics due to the suppression of parasitic source/drain resistance and the ultra-shallow source/drain layers.

Self-aligned Split Gate Electrodes Fabricated on Suspended Carbon Nanotubes

ABSTRACTWe describe the fabrication of self-aligned split gate electrodes on suspended multiwalled carbon nanotube structures. A suspended multiwalled carbon nanotube structure was used as an evaporation mask for the deposition of metal electrodes resulting in the formation of discontinuous wire deposition. The metal deposits on the nanotubes are removed with lift-off due to the poor adhesion of metal to the nanotube surface. Using Al sacrificial layers, it was possible to fabricate self-aligned contact electrodes and control electrodes nanometers from the suspended carbon nanotubes with a single lithography step. It was also shown that the fabrication technique may also be used to form nano-gaped contact electrodes. The technique should prove useful for the fabrication of nano-electromechanical systems.

Self-aligned Split Gate Electrodes Fabricated on Suspended Carbon Nanotubes

ABSTRACTWe describe the fabrication of self-aligned split gate electrodes on suspended multiwalled carbon nanotube structures. A suspended multiwalled carbon nanotube structure was used as an evaporation mask for the deposition of metal electrodes resulting in the formation of discontinuous wire deposition. The metal deposits on the nanotubes are removed with lift-off due to the poor adhesion of metal to the nanotube surface. Using Al sacrificial layers, it was possible to fabricate self-aligned contact electrodes and control electrodes nanometers from the suspended carbon nanotubes with a single lithography step. It was also shown that the fabrication technique may also be used to form nano-gaped contact electrodes. The technique should prove useful for the fabrication of nano-electromechanical systems.

Gated field emitter arrays

The successful fabrication of field emission (FE) devices is directly related to process simplicity and device performance, which depends to a large extent on the tip material and emitter geometry. On the other hand, these characteristics are the most important issues influencing industrial applicability of the FE devices. In most typical solutions single emitter cells consist of a sharp tip located in the hollow, with the tip apex surrounded by a gate. The fabrication process described here is simple and allows self-aligned gate electrode formation. The field emission of the emitter tips is supported by a 50-nm diamond-like-carbon (DLC) film formed by chemical vapor deposition.