A Reduced Mask-Count Technology for Complementary Polycrystalline Silicon Thin-Film Transistors With Self-Aligned Metal Electrodes

Abstract

The inexpensive glass substrate for building conventional low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) imposes a ceiling on the TFT processing temperature. This results in a reduced efficiency of dopant activation and a high source/drain series resistance. A technique based on aluminum-induced crystallization of amorphous silicon has been applied to fabricate TFTs with low-resistance self-aligned metal electrodes (SAMEs). While at least two masked implantation steps are typically used for constructing the doped source and drain regions of conventional n- and p-channel TFTs in a complementary metal-oxide-semiconductor circuit technology, it is currently demonstrated that complementary SAME poly-Si TFTs can be constructed using a combination of a masked and a blanket source and drain implantation steps. The decrease in mask count reduces process complexity and cost. Control of ion channeling is the enabling factor behind the successful demonstration of the technology.