Salicide Process Research Articles

The investigation of key technologies for sub-0.1-μm CMOS device fabrication

The fabrication of sub-0.1-/spl mu/m CMOS devices and ring oscillator circuits has been successfully explored. The key technologies include: lateral local super-steep-retrograde (SSR) channel doping with heavy ion implantation, 40-nm ultrashallow source/drain (S/D) extension, 3-nm nitrided gate oxide, dual p/sup +//n/sup +/ poly-Si gate electrode, double sidewall scheme, e-beam lithography and RIE etching for sub-0.1-/spl mu/m poly-Si gate pattern, thin and low sheet resistance SALICIDE process, etc. By these innovations in the technologies, high-performance sub-0.1-/spl mu/m CMOS devices with excellent short-channel effects (SCEs) and good driving ability have been fabricated successfully; the shortest channel length is 70 nm. 57 stage unloaded 0.1-/spl mu/m CMOS ring oscillator circuits exhibiting delay 23.8 ps/stage at 1.5 V, and 17.5 ps/stage and 12.5 ps/stage at 2 V and 3 V, respectively, are achieved.

Gaseous Impurities in Co Silicidation: Impact and Solutions

With the application of a Co salicide process in deep submicrometer integrated circuits manufacturing, the potential benefit of its linewidth independent sheet resistance could be hindered due to the interaction of traces of gaseous impurities from different sources with silicide formation. In this work, we first analyze in situ the thermal desorption behavior of various dielectric and metal layers encountered in Co salicide process, by using the rapid thermal processing tool-atmospheric pressure ionization mass spectrometry. Based on these results as well as information from the literature, the detrimental impact of gaseous impurities (mainly and has been analyzed. The key facts are that Si has a stronger chemical affinity to O than Co, and the interaction of Co and Si oxide occurs only with great difficulty. We also argue that impurities from thermal desorption can have a stronger impact to the silicidation (edge thinning effect) compared to the impurities already in the processing ambient, due to its strong and direct interaction to the adjacent Co/Si interface. The fundamental principle of a technical solution is that the process should prevent O from coming into the Co/Si interface, and/or should be capable of removing the Si oxide already there. A few solutions reported in literature, including depositing Co at elevated temperatures, Co with reactive or nonreactive capping, and the use of Co(Ti) alloys, are analyzed. © 2001 The Electrochemical Society. All rights reserved.

A high-efficiency thin-film SOI power MOSFET having a self-aligned offset gate structure for multi-gigahertz applications

A highly efficient radio-frequency (RF) thin-film SOI power MOSFET having a self-aligned offset gate structure has been fabricated, It was fabricated using a self-aligned offset gate structure based on a lightly doped drain (LDD) structure to reduce the on-resistance and thus increase the power-added efficiency. The target breakdown voltage was 10 V, and the fabricated device had a breakdown voltage of 14.3 V. The on-resistance of a thin-film SOI power MOSFET using titanium salicide process was lower than that of the one fabricated using a tungsten polycide process. The cutoff frequency and maximum oscillation frequency of the titanium salicide process were 17 and 24 GHz, respectively. Its power-added efficiency at 2 GHz was 67% and its saturation output power was 20 dBm when the drain supply voltage was 3.0 V. Its power-added efficiency at 5.8 GHz was 53% and its saturation output power was 19 dBm when the drain supply voltage was 3.0 V. The dc and RF performances of the power MOSFET fabricated using the titanium salicide process were better than those of the one fabricated using the tungsten polycide process.

Structural relationship of polycrystalline cobalt silicide lines to (001) silicon substrate and their thermal stability

We have investigated the crystalline quality of 0.6–1.2 μm poly-CoSi 2 lines, formed on (001) silicon by a standard salicide process. The microstructure of silicide grains has been investigated by TEM and HRTEM techniques and related to their location inside the strip. The grains at the centre of the line were randomly oriented with respect to the substrate unlike at the edges, where some interesting epitaxial relationships were detected. Selected area diffraction (SAD) analyses on the line section indicated the presence of both A- and B-type epitaxial regions even inside the same grain, whose interface to silicon lies along the (1, 1 ̄ ,1) planes. In these regions, high-resolution transmission electron microscopy (HRTEM) analyses have shown misfit dislocations inserted along the (111) planes to compensate the lattice mismatch. High temperature anneals mainly deteriorate the line edges with serious damage to their electrical performance.

Advanced salicided 4 Mbit flash memory array with borderless contacts

System on chip development requires many different devices to be integrated on the same chip and a high compatibility between CMOS logic core process and added modules. The self-aligned silicide process coming from high performance logic gives in a Flash memory array several opportunities: to take advantage of low word-line resistance, to eliminate any metal strap in the array reducing potential process defectivity thus improving devices yield. On the other hand, the salicidation of Flash memory requires at the same time to achieve a continuous low resistance line on the no-flat array topography (due to the double poly stacked gate memory cell structure) and to avoid any junction leakage risk, that might modify the device performances. The aim of this work is to demonstrate the feasibility and compatibility of advanced Ti salicide process with Flash memory array embedded in a high performance logic. The feasibility has been proven on a classical NOR 4 Mbit stand-alone memory test chip processed in 0.25 μm technology, that furthermore asks for borderless contacts.

The reaction of Co and Si1−xGex for MOSFET with poly-Si1−xGex gate

Abstract The effects of Ge on the interfacial reaction between Co and poly-Si1−xGex materials were studied. Poly-Si1−xGex layers prepared at 580°C by ultra-high vacuum chemical molecular epitaxy (UHVCME) system were subjected to Co silicidation at various rapid thermal annealing (RTA) temperatures ranging from 500 to 900°C. From X-ray diffractometry (XRD), Co(Si1−yGey) cubic structure was formed with RTA temperature ranging from 500 to 800°C for x=0.09, while CoSi2 was formed at 900°C. However, for x=0.21, Co(Si1−yGey) persisted even after 900°C RTA annealing, and CoSi2 was not found. These results indicate that Ge atoms retard the formation of CoSi2. As a result, the RTA temperature needed to obtain low sheet resistance has to be increased with increasing Ge content. Finally, p-channel metal-oxide-semiconductor (MOS) transistors with poly-Si1−xGex-gate have been successfully integrated with Co salicidation process.

A Self-Aligned Silicide Process for Thin Silicon-on-Insulator MOSFETs and Bulk MOSFETs with Shallow Junctions

AbstractWe discuss a modified self-aligned silicide (salicide) process that uses a silicon cap to reduce the substrate silicon consumption by 50% as compared with a conventional salicide process. We have used a metal-silicon mixture to form the metal-rich phase reliably in the first anneal. After etching the unreacted mixture we deposit a silicon cap. This forces the metal to react with the silicon cap as well as with the substrate during the second anneal, thus minimizing silicon consumption from the substrate. The unreacted portion of the silicon cap is selectively etched, leaving a structure with a raised source and drain. We expect this process to be useful for forming silicide on shallow junctions and thin SOI films, where silicon consumption is constrained.

Direct Formation of C54 Phase on the Basis of C40 TiSi2 and Its Applications in Deep Sub-Micron Technology

ABSTRACTA simple and novel salicidation process applying pulsed laser annealing as the first annealing step was used to induce TiSi2 formation. Both Raman spectroscopy and transmission electron microscope results confirm the formation of a new phase of Ti disilicide, the pure C40 TiSi2 after laser irradiation. Direct C54 phase growth on the basis of C40 template bypassing the C49 phase is accomplished at the second annealing temperature as low as 600°C. Line width independent formation of the C54 phase was observed on patterned wafers using this salicidation process and “fine line effect” is thus eliminated.

Improved NiSi salicide process using presilicide N/sub 2//sup +/ implant for MOSFETs

An improved Ni salicide process has been developed by incorporating nitrogen (N/sub 2//sup +/) implant prior to Ni deposition to widen the salicide processing temperature window. Salicided poly-Si gate and active regions of different linewidths show improved thermal stability with low sheet resistance up to a salicidation temperature of 700 and 750/spl deg/C, respectively. Nitrogen was found to be confined within the NiSi layer and reduced agglomeration of the silicide. Phase transformation to the undesirable high resistivity NiSi/sub 2/ phase was delayed, likely due to a change in the interfacial energy. The electrical results of N/sub 2//sup +/ implanted Ni-salicided PMOSFETs show higher drive current and lower junction leakage as compared to devices with no N/sub 2//sup +/ implant.

Process variations in use for the first generations of FRAM® memory products

Ferroelectric memories have been firmly established commercially over the past decade. This paper presents the process variations used by Ramtron for its portion of the worldwide FRAM output and discusses the reasons why the particular process was chosen for each case. The first ferroelectric memory produced in volumes exceeding millions of units was the FM1208 4Kb parallel part in 1992. The exact process for the fabrication of this part at the wafer level involves a combined salicide and silicide process for the successful integration of ferroelectric materials. Furthermore, a special packaging technique is employed to minimize the effect of hydrogen and stress in the plastic packaging mold compound. Current generations of FRAM no longer have the requirement for special processing or materials at assembly. Current generation IC card products are clearly state-of-the art as programmed contents of the chip are easily retained through the card packaging process. Test and quality methods and results are reviewed.

Low temperature process for strontium bismuth tantalate thin films

As CMOS dimensions shrink so does the limitation on total thermal budget for processing. For 0.18 μm design rules, the junction depth and the salicide process requirements limit the maximum processing temperature to below 700°C, preferably down to 650°C. For FeRAMs, this results in limitation on the thermal budget available for the crystallization of ferroelectric films. SBT and SBTN films have been generally annealed at 700°C or higher. Lowering the crystallization temperature down to 650°C requires the suppression of fluorite phase in order to obtain good ferroelectric performance. We have developed a CSD based low temperature process for SBT films yielding excellent ferroelectric properties. Several materials and process parameters have been optimized to suppress the fluorite phase. These include film stoichiometry and thickness, anneal ambient and ramp rates, UV energy and precursor solvents. In this paper we present a complete 650°C process for SBT thin films, highlighting process modifications and their effect on ferroelectric performance.

Precision Resistor Integration into a Submicron Silicided Complementary Metal Oxide Semiconductor Technology

This paper examines the process issues of integrating a precision resistor feature into an existing salicided complementary metal oxide semiconductor technology. The resistor features are created by selectively blocking salicide formation with a thin nitride layer that must be compatible with the existing device and salicide processes. The integrity of the blocking layer during the HF‐based salicide preclean is of special concern. Methods to monitor and control the properties of the thin nitride blocking layer have been developed. © 2000 The Electrochemical Society. All rights reserved.

Void formation in titanium desilicide/p + silicon interface: impact on junction leakage and silicide sheet resistance

We have observed the formation of voids at the interface of TiSi 2/p +-Si after the titanium-salicidation process in a deep-sub-micron CMOS technology. In our study, most of the voids occurred at the intersection of the polycrystalline TiSi 2 grain boundary with the p + Si substrate and had an extended defect into the p + Si substrate. In some cases, for voids that were not located at the TiSi 2 grain boundary, the substrate defects extended from the void/p +-Si interface into the silicide film, resulting in micro-twin defects. In addition, discrete and isolated defects were found at the bird’s beak tips, which are most likely due to dislocation loops. However, its density was very low. Our investigation shows that void formation is relatively sensitive to the BF 2 + implant and p + junction annealing temperature, and can be completely avoided by subjecting the p + junctions to a high temperature anneal at 850°C for 45 min prior to the salicidation process. We attribute these voids to the fluorine-related precipitates, in which the fluorine is from the BF 2 + ion implantation. It is believed that the formation of substrate defects is the root cause of high junction leakage observed in the pMOSFET devices, and the leakage can be substantially reduced by 1–2 orders of magnitude with the extra high temperature anneal. On top of that, the distribution of the sheet resistance of the Ti-salicided p +-Si becomes tighter.

Study of CoSix Spike Leakage for 0.1-um CMOS

ABSTRACTWe have clarified a new leakage mechanism in Co salicide process for the ultra-shallow junctions of 0.1-um CMOS devices and revealed the optimum Co salicide process conditions for minimizing the leakage current. We found that leakage currents generate from many localized points that are randomly distributed in the junction area, and not from the junction edge. We successfully verified our localized leakage model using Monte Carlo simulation. We identified abnormal CoSix spiking growth under the Co silicide film, as being the origin of the localized leakage current. These CoSix spikes grow rapidly only during annealing between 400°C and 450°C when Co2Si phase is formed. These spikes never grow during annealing at over 500°C, and decrease with high temperature annealing over 500°C. A minimum leakage current can be achieved by optimized annealing at between 800°C and 850°C for 30 sec. This is because a trade-off between reducing the CoSix spikes and preventing the Co atom diffusion from Co silicide film to Si substrate, which begins at annealing above 900°C.

Salicides: materials, scaling and manufacturability issues for future integrated circuits ( invited)

In this paper we present an overview of the development of advanced salicide processes at Texas Instruments, addressing both Ti and Co salicides. Scaling issues, such as sheet resistance of deep sub-micron structures for Ti salicide and diode leakage on shallow junctions for Co salicide, are discussed, as well as processes developed to overcome these issues. The key material aspects controlling these variables are reviewed, such as Ti silicide phase formation and transformations and mechanisms of direct formation of C54 TiSi 2, which control sheet resistance, and silicide–silicon interface characteristics for Co salicide, impacting diode leakage. Implementation and manufacturability aspects are also discussed. We present advanced Ti and Co salicide processes with manufacturing and high yield capability demonstrated for sub-0.25 μm CMOS technologies. Process modifications that extend the applicability of these salicides to 0.1 μm CMOS are also presented.

Integration Challenges for Advanced Salicide Processes and their Impact on CMOS Device Performance

ABSTRACTCoSi2 has emerged as the silicide of choice for 0.18μm CMOS technologies and below. Robustness and scaling-performance of an integrated CoSi2-module, however, is shown to critically depend upon careful optimization of each individual process-step. The impact of surface-preparation, capping layer, initial Co-thickness and thermal processing will be discussed. The scalability of an optimized process meeting all major requirements for application to ULSI devices is demonstrated for gate-length down to 60nm.

Growth behavior and thermal stability of epitaxial CoSi2 layer from cobalt–carbon films on (100) Si substrate

A uniform epitaxial CoSi2 layer was grown on (100) Si substrate by rapid thermal annealing at 800 °C in N2 ambient without capping layers from an amorphous cobalt-carbon film. The amorphous cobalt-carbon film was deposited on Si substrate by the pyrolysis of cyclopentadienyl dicarbonyl cobalt, Co(η5–C5H5)(CO)2, at 350 °C. The discrete epitaxial CoSi2 layers with {111} and (100) faceted interfaces were formed on (100) Si substrate at the initial stage of reaction between Co and Si. Annealing at elevated temperatures lowered the roughness of the CoSi2/Si interface. The leakage current measured on the junction, fabricated with the epitaxial CoSi2 layer and annealed at 1000 °C for 30 s, was as low as that of the as-fabricated junction without silicide. The result indicates that epitaxial (100) CoSi2 is thermally stable at temperatures even above 1000 °C and has potential application to the salicide process in subhalf micron devices.

Effects of ramp-up rates on the salicide process

Increases in the sheet resistance of TiSi2 with a decreasing linewidth has been attributed to incomplete transformation from high resistance C49–TiSi2 phase to the desired low resistance C54–TiSi2 phase. In this article, we investigate the effects of increasing the ramp up rate of the first rapid thermal anneal (RTA1) in the salicide process. Electrical testing and micro-Raman spectroscopy were used to investigate the C49-to-C54 phase transformation on poly lines with different linewidths. Samples were annealed with two different ramp-up rates in RTA1. From micro-Raman spectra, it is observed that increased ramp-up rate during RTA1 results in more C54–TiSi2 formed during the second rapid thermal anneal (RTA2). It is also shown that higher ramp-up rates result in lower sheet resistance for deep submicron poly lines.

Spectroscopic ellipsometry investigation of silicide formation by rapid thermal process

Titanium, cobalt, and nickel silicides have been considered as self-aligned silicides (salicides) for contact and interconnect metallization in ultralarge scale integrated circuits. A CoSi2 salicide process using TiN or Ti capping, which is superior to the conventional cobalt salicidation, has been found to be a good solution for producing a lower sheet resistance value and a tighter sheet resistance distribution. In this work cobalt silicidation with and without a TiN and Ti cap has been performed in temperature range of 300–800 °C. In order to extensively study the phase sequence of silicide formation, a spectroscopic ellipsometry (SE) technique has been used to characterize the thin silicide films. The measurement of the optical properties and thicknesses of thin cobalt, stacked TiN/Co, and cobalt silicide layers has been compared with four point probe measurements. Also, a technique employing a SE optical method has been successfully developed to measure the thickness of thin Co and CoSi films and the selective etch rates of TiN and CoSi, which showed 0.45 and 0.009 nm/s, respectively, for TiN capped Co silicidation. The results obtained by the SE nondestructive technique are also compared with the results of Rutherford backscattering spectrometry.

Effect of Mo doping on accelerated growth of C-54 TiSi2: Evidence for template mechanism

The phase sequence of the rapid thermal processing induced reaction at T=650 °C has been studied by a combination of high resolution transmission electron microscopy and image simulations. We found that pre-amorphization of poly-Si substrates does not change the reaction path, i.e., Ti5Si4 and C-49 TiSi2 phases were formed with the latter growing upon further annealing. In the Mo doped poly-Si/Ti system the C-54 TiSi2 phase forms along with Ti5Si4 and two Mo silicide phases, MoSi2 and Mo5Si3; no C-49 TiSi2 was observed. We provide direct evidence that the Ti–Si reaction in the Mo doped system follows the template mechanism with MoSi2 and Mo5Si3 based phases acting as template phases for accelerated growth of C-54 TiSi2. Direct formation of C-54 TiSi2 at lower temperatures bypassing C-49 TiSi2 is very promising for application of the Ti salicide process in the future generation of deep-submicron complementary metal–oxide–semiconductor devices.