Abstract

ABSTRACTCoSi2 has emerged as the silicide of choice for 0.18μm CMOS technologies and below. Robustness and scaling-performance of an integrated CoSi2-module, however, is shown to critically depend upon careful optimization of each individual process-step. The impact of surface-preparation, capping layer, initial Co-thickness and thermal processing will be discussed. The scalability of an optimized process meeting all major requirements for application to ULSI devices is demonstrated for gate-length down to 60nm.

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