Salicide Process Research Articles

Salicidation process for submicrometre gate MOSFETfabrication using a resistless electron beam lithography process

Recently, a novel silicide direct write electron beam lithography (SiDWEL) process has been developed in order to achieve high resolution (50 nm) silicide structures without the need for any supplementary annealing step. This new lithography technique is used to fabricate N-type MOSFET devices with platinum silicide gates. The fabrication uses a mix and match approach to combine the SiDWEL process with conventional MOSFET fabrication techniques.

Cobalt sputtering target and sputter deposition of Co thin films for cobalt silicide metallization

CoSi 2 is considered an alternative to TiSi2 for use as a contact in ultralarge scale integration due to its low resistivity, excellent chemical stability and lower formation temperature. Sputter deposition of Co thin films is one of the crucial steps in the cobalt salicide (a self-aligned silicide) process. One major problem with sputter deposition of Co thin films is that Co is a ferromagnetic material and is difficult to sputter. The dc magnetic field transmitted through a ferromagnetic material from one side to another is called the pass-through flux (PTF). In this study, the effects of target PTF and sputtering process parameters such as Ar pressure and sputtering power on the sputter process were studied. Co targets with PTF% of 65% (high PTF), 53% (medium PTF) and 32% (low PTF) were sputter tested. The sputter deposition rate, I–V characteristics, film sheet resistance and film uniformity were measured under various sputter conditions. The study indicated that, in magnetron sputtering of Co, a high magnetic flux intensity could be obtained by using a high PTF target that allowed maximum magnetic flux to permeate through the target. The I–V characteristics of different PTF targets followed the typical I=KVn relationship of dc planar magnetron sputtering. The exponents in the equation, n, increased with increasing target PTF%, indicating the sputtering impedance decreased with increasing target PTF%. The target with the highest PTF% demonstrated the best performance and film uniformity. Rapid thermal processing (RTP) was carried out to form cobalt silicides at temperatures between 300 and 850 °C in Ar atmosphere for various times. The sheet resistance of the Co and cobalt silicide films produced was monitored by a four-point probe before and after the RTP. The sheet resistance decreased significantly after annealing at 600 and 700 °C due to formation of CoSi2, which has lower resistivity. The significant increase in sheet resistance after annealing at 400 and 500 °C was attributed to formation of the CoSi phase. For the 16 nm thick Co film, a sheet resistance of 3.2 Ω/sq was obtained after RTP at 600 and 700 °C.

A Novel Clean Ti Salicide Process Using Grooved Gate Structure

It is demonstrated that dry etching and Ar sputtering for Si surface cleaning cause phase transition failures of TiSi2 and degradation of the resistivity. We propose a Ti self-aligned-silicide (salicide) process using a grooved gate structure. In this technique, poly-Si is patterned by an oxide mask. The oxide layer protects the gate surface from contamination by dry etching for sidewall formation. Before Ti deposition, the poly-Si surface is not sputtered by Ar to clean the surface. As a result, TiSi2 agglomeration was suppressed drastically in comparison with the conventional gate structure.

A new leakage mechanism of Co salicide and optimized process conditions [for CMOS

We have clarified a new leakage mechanism in Co salicide process for the ultrashallow junctions of 0.1-/spl mu/m CMOS devices and revealed the optimum Co salicide process conditions for minimizing the leakage current. We found that leakage currents flow from many localized points that are randomly distributed in the function area. We successfully verified our localized leakage model via Monte Carlo simulation. We identified abnormal CoSi/sub x/ spikes under the Co silicide film, as being the origin of the localized leakage current. These CoSi/sub x/ spikes grow rapidly only during annealing between 400 and 450/spl deg/C for 30 s when Co/sub 2/Si phase is formed. These spikes never grow during annealing at over 500/spl deg/C, and decrease with high temperature annealing. A minimum leakage current results by optimized annealing at between 800 and 850/spl deg/C for 30 s. This is because a trade-off exists between reducing the CoSi/sub x/ spikes and preventing the Co atom diffusion from Co silicide film to Si substrate, which begins at annealing above 900/spl deg/C.

Arsenic-Only Preamorphization Process Extension For TiSi2 Formation Down to 65-nm Gate Lengths

AbstractThe scalabilty of the titanium self-aligned silicide (Salicide) process is one of the main issues for sub-quarter micron technologies. The major difficulty is to achieve a low sheet resistance for very narrow polysilicon lines and highly doped S/D regions, without degrading the transistor performance. A preamorphization implant (PAl) performed before the titanium deposition, can achieve a low Ti silicide sheet resistance (<10 Ohms/sq) down to 0.1 Vim gate lengths [1]. Nevertheless, it has been recently reported that PAI should not be sufficient to achieve low silicide sheet resistance for narrower gate widths (< 0.1 µm) [2]. In this work, an extension of the PAI process down to 0.065µm poly-Si lines width, by only using an arsenic implant is presented, achieving a very low sheet resistance value (∼5 Ohms/sq). This result has been obtained by optimizing both the arsenic implant conditions and the silicon surface cleaning. Moreover, a large statistical analysis of the arsenic PAI process impact on 0.25µm device performances has been done, showing that a defectivity of the NMOS Ioff leakage current can appear if preamorphization implant conditions are not optimized.

Epitaxial Growth and Thermal Stability of CoSi2 Layer on (100) Si from Co-C Films without Capping Layer

AbstractA uniform epitaxial CoSi2 layer was grown on (100) Si substrate by rapid thermal annealing at 800°C in N2 ambient without capping layers from an amorphous cobalt-carbon film. The amorphous cobalt-carbon film was deposited on Si substrate by the pyrolysis of cyclopentadienyl dicarbonyl cobalt. Co(η5-C5H5)(CO)2. at 350°C. The leakage current measured on the junction, fabricated with the epitaxial CoSi2 layer and annealed at 1000°C for 30 s. was as low as that of the as-fabricated junction without silicide. indicating that epitaxial (100) CoSi2 is thermally stable at temperatures even above 1000°C and has a potential applicability to the salicide process in sub-half micron devices.

The Future Of Silicide For CMOS Contacts

AbstractThis paper examines the challenges for silicide contacts in current and future CMOS technologies and assesses the capability of TiSi2 and related materials, as well as CoSi2, to meet the technology requirements. Specific issues such as maintaining low resistance in narrow lines, source/drain silicon consumption, and silicide thermal budget, are discussed. In this regard we evaluate the salient features of the basic titanium salicide process, and variations such as alloying, implantation, selective CVD, and laser silicidation. Data are presented from recent experiments to assess progress in each approach towards meeting the necessary goals. Finally, projections of the future of silicide processing are given.

Thermal Studies on Stress-Induced Void-Like Defects in Epitaxial-CoSi2 Formation

AbstractWe report experimental findings on the thermal-induced stress-voiding observed during epitaxial CoSi2 formation on patterned Si(100) wafers associated with the Co/Ti-interposing layer scheme [1–6]. The first rapid thermal process (RTP) in a typical SALICIDE process was studied by varying the temperature and the RTP ramp-up rate. Based on ex-situ cross-sectional transmission electron microscopy (XTEM), crystal defects were observed at shallow trench isolation (STI)/Si and gate spacer/Si edges after annealing at temperatures greater than 520°C. In addition, isothermal anneals for various time periods resulted in increased encroachment of an ultra-thin CoSi2-phase at the STI/Si edge. Higher temperature anneals also resulted in a corresponding increase in void size. In addition, higher ramp-up rates led to a thicker CoSi2 “pocket” film at the tensile-stressed STI/Si edge, aligned epitaxially along the {111}-habit planes. Our attempts to bypass the CoSi formation in order to alleviate the anomalous Si diffusion was found to be irrelevant to the voiding issue, due to the inherent nature of this film stack system to nucleate CoSi2 as the first phase. By comparing our experimental observations of voiding with Hu's analysis of the trench isolation stress fields, we found good agreement with the predicted stress field distribution in the active Si and STI/Si edge with the locations of void nucleation. The anomalously large stress induced is still not known, but can be attributed to the encroaching CoSi2 film which tends to realign epitaxially along the STI/Si interface.

Advanced salicides for 0.10 μm CMOS: Co salicide processes with low diode leakage and Ti salicide processes with direct formation of low resistivity C54 TiSi2

The scaling of CMOS technologies to 0.10 μm and beyond imposes increasingly demanding constraints to self-aligned silicide (salicide) processes. For high performance devices, it is essential that salicide processes achieve low gate and source-drain sheet resistance as well as low silicide to source-drain diffusion contact resistance, and maintain low junction leakage. This becomes increasingly difficult as junction depths and linewidths are scaled. In this paper we present an overview of the development of advanced Ti and Co salicide processes, with implementations into a high performance 0.10 μm complementary metal-oxide-semiconductor (CMOS) technology. For Co salicide, the main scaling issue is diode leakage on shallow junctions. We show that the use of pre-amorphization implants or a pre-Co deposition sputter etch improves diode leakage distributions, but fails to eliminate high leakage outliers. Co deposition temperature and rapid thermal processing (RTP) variables were found to have a strong effect on diode leakage, with optimization of either one resulting in tight low leakage distributions on shallow junctions. For conventional Ti salicide processes, the main scaling issue is sheet resistance on narrow lines due to incomplete high resistivity C49 TiSi2 to low resistivity C54 TiSi2 transformation. We present X-ray diffraction (XRD) and high resolution transmission electron microscopy (HRTEM) studies that indicate that direct growth of C54 TiSi2 bypassing the C49 phase is achieved at low temperatures on polycrystalline or amorphous Si with the addition of Mo impurities, eliminating the narrow line effect. The mechanism is demonstrated to be nucleation of MoSi2 and an unidentified phase at the Ti/Si interface, followed by epitaxial growth of C54 TiSi2 on these templates. Ti salicide processes with Mo impurities were evaluated, demonstrating an optimized one-step RTP process combining Mo and pre-amorphization implants that maintains low sheet resistance to 0.06 μm gate lengths. Successful implementations into a 0.10 μm flow were achieved both for optimized Co salicide or Ti salicide processes.

Co salicide technology

Ti, Pt, Ni, and Co salicide processes are applied to 0.1-µm CMOS devices and the problems and possibilities are discussed. Co salicide technology is an especially promising process. The mechanisms of the resistance fluctuations and junction leakage current appearing in the conventional Co salicide processes are identified and solution methods are presented. © 1998 Scripta Technica, Electron Comm Jpn Pt 2, 81(11): 26–33, 1998

ESD protection for slew-rate-controlled output buffer in a 0.5 μm CMOS SRAM technology

A new ESD protection design by using the well-coupled field-oxide device (WCFOD) is proposed to protect the slew-rate-controlled output buffer in a 0.5 μm P-well/ N-substrate CMOS SRAM technology. The ESD transient voltage is coupled to the P-well of the ESD protection field-oxide device through a parasitic capacitor to trigger on the bipolar action of the field-oxide device. The ESD trigger voltage of the WCFOD can be lowered to below the snapback-breakdown voltage of the output NMOS transistor, so it provides effective ESD protection for the slew-rate-controlled output transistors without causing any degradation on the circuit performance. The coupling capacitor is made by inserting a poly layer right under the wire-bonding metal pad without the increase of layout area. A modified WCFOD structure is also proposed for output ESD protection in deep-submicron CMOS technology with polycide or salicide processes. Three conventional output ESD protection designs with the series resistor, the double-diode structure, and the field-oxide device, are also made for comparison. Five test chips with the same 256 K SRAM core but only different output ESD protection designs have been fabricated in a same wafer to practically verify the ESD protection efficiency of this proposed WCFOD and modified WCFOD structures.

The impact of MOSFET technology evolution and scaling on electrostatic discharge protection

MOSFET (metal-oxide silicon field effect transistor) evolution and technology scaling impacts electrostatic discharge (ESD) protection networks, design and strategy. The continous evolution of semiconductor processing forces new issues to arise for each technology generation and the evolution of MOSFET structures in each generation requires re-addressing of the scaling implications on ESD robustness. This paper addresses the impact of semiconductor technology evolution and scaling of the epitaxial film, well design, isolation technology, MOSFET junctions, silicides, and interconnects on ESD robustness. The scaling of the epitaxial film thickness and p++ vs p− substrate influences the ESD robustness of n-channel MOSFET and diode-based ESD protection networks. ESD diode elements show a 2× to 3× improvement in thin p− epitaxy on a p++ wafer compared to p−substrates. The evolution from diffused wells to MeV-implanted retrograde well designs have shown that the parasitic vertical bipolar transistor plays a lesser role in ESD protection networks compared to the diode action. A 3× HBM (human body model) ESD improvement is demonstrated using advanced high dose MeV retrograde well implants. Isolation technology has an influence on the high voltage electrical parametrics, lateral parasitics, thermal transport and semiconductor process integration with the MOSFET junction and silicide film. The transition from LOCOS to STI (shallow trench isolation) significantly altered the electrical parametrics, failure mechanisms, and ESD networks. The MOSFET-junction evolution from Ldd, dual-Ldd, abrupt junctions to “extension implants” and how this influenced integration and ESD robustness is discussed. MOSFET junctions, salicide, and STI integration issues, such as STI pull-down, can influence the ESD robustness of ESD diode structures. Althernative salicide processes (e.g. cobalt), deep B11 implants and novel poly-silicon-bound diode structures demonstrate 3× improvement in HBM ESD robustness. As technology transitions from aluminum- to copper-based interconnect systems, interconnect wire (2× improvement) and via (3× improvement) ESD improvements are demonstrated. As a result of power supply scaling, the impact of technology scaling on ESD networks, peripheral I/O driver circuits and receiver networks, and how it influences the ESD protection of advanced semiconductor chips is shown. Power-supply scaling, noise issues and multichip systems has led to increasing complexity and importance of sequence-independent ESD networks, ESD networks between power supplies and ESD power clamps. Receiver and I/O driver designs have also evolved due to the MOSFET dielectric scaling and ESD robustness requirements. Technology generation evolution of peripheral driver circuits evolution demonstrates the need for local resistor ballasting of driver circuits. With MOSFET scaling, receiver circuit pass transistors, keeper feedback and zero-Vt devices introduce new ESD issues and receiver design complexity. MOSFET scaling requires ESD power clamps across core and peripheral supplies to reduce the current loop impedance for high frequency applications. MOSFET scaling also has led technology to have a future interest in high-frequency semiconductor devices, such as rf-CMOS, silicon-on-insulator, and SiGe-based devices. Novel SOI ESD networks, such as polysilicon-bound diodes and body- and gate-coupled SOI ESD networks, demonstrate excellent ESD results in advanced CMOS-on-SOI technologies.

Comparative evaluation of Ti salicide and Co salicide processes for CMOS devices

Optimized Ti salicide and Co salicide module processes were comparatively evaluated. The pre-amorphization process and Si intermixing process for TiSi2 formation were effective methods for maintaining low sheet resistance in narrow regions. However, in the case of the Si intermixing process, the threshold voltage of PMOS devices was unstable. With the pre-amorphization process for Ti salicide, a stable threshold voltage was obtained in CMOS devices. In addition, a low sheet resistance in the narrow regions was maintained in the Co salicide process, without the pre-amorphization process. In the contact process, CoSi2 was not easily etched off by the dry etching gas used for contact hole formation. By using the optimized pretreatment method with low sputtering yield, Co salicide will have wider process windows than Ti salicide. © 1998 Scripta Technica, Electron Comm Jpn Pt 2, 81(8): 26–31, 1998

A low thermal budget self-aligned Ti silicide technology using germanium implantation for thin-film SOI MOSFET's

In this paper, a titanium salicide technology with a very low thermal annealing temperature using germanium implantation for thin film SOI MOSFET's is investigated in detail. Ti silicide formation on the amorphous silicon generated by germanium implantation is studied. Compared to the conventional Ti salicide process, the Ti silicidation temperature is significantly lowered and the silicide depth is well controlled through the pre-amorphized layer. Therefore, the potential problems of the salicide process for SOI MOSFET's such as lateral voids, dopant segregation, thermal agglomeration, and increase of resistance on narrow gate are suppressed by germanium implantation. With the Ge pre-amorphization salicide process, a very low silicide contact resistance is obtained and sub-0.25-/spl mu/m SOI MOSFET's are fabricated with good device characteristics.

Scaled CMOS technologies with low sheet resistance at 0.06-μm gate lengths

A novel Ti self-aligned silicide (salicide) process using a combination of low dose molybdenum and preamorphization (PAI) implants and a single rapid-thermal-processing (RTP) step is presented, and shown to be the first Ti salicide process to achieve low sheet resistance at ultrashort 0.06-μm gate lengths (mean=5.2 /spl Omega//sq, max=5.7 /spl Omega//sq at 0.07 μm; mean=6.7 /spl Omega//sq, max=8.1 /spl Omega//sq at 0.06 μm, TiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> thickness on S/D=38 nm), in contrast with previous Ti salicide processes which failed below 0.10 μm. The process was successfully implemented into a 1.5 V, 0.12-μm CMOS technology achieving excellent drive currents (723 and 312 μA/μm at I/sub OFF/=1 nA/μm for nMOS and pMOS, respectively).

Optimization of Ti and Co Self-Aligned Silicide RTP for 0.10 μm Cmos

ABSTRACTAs CMOS technologies are scaled to 0.10 μm and beyond, self-aligned silicide (salicide) processes find difficult challenges. As junction depths and linewidths are scaled, achieving both low sheet resistance and low contact resistance maintaining low diode leakage becomes increasingly difficult. In this paper we present studies of Ti and Co salicide processes implemented into a 0.10 μm CMOS technology. We show that both for Ti and Co, the optimization of RTP parameters plays a crucial roll in achieving a successful implementation. For Co salicide, optimization of RTP conditions results in elimination of shallow junction leakage (its main scaling problem). Two-step RTP and one-step RTP Ti salicide processes are compared, showing the advantages of one-step RTP. The RTP process windows for low resistance narrow gates (the main scaling issue for Ti salicide) are analyzed. Processes with pre-amorphization, with Mo doping and with a combination of both are compared. An optimal process using Mo and preamorphization implants and one-step RTP is shown to result in excellent device characteristics and low resistance to 0.06 μm gates.

Optimization of Ti and Co Self-Aligned Silicide RTP for 0.10 μm CMOS

ABSTRACTAs CMOS technologies are scaled to 0.10 μm and beyond, self-aligned silicide (salicide) processes find difficult challenges. As junction depths and linewidths are scaled, achieving both low sheet resistance and low contact resistance maintaining low diode leakage becomes increasingly difficult. In this paper we present studies of Ti and Co salicide processes implemented into a 0.10 μm CMOS technology. We show that both for Ti and Co, the optimization of RTP parameters plays a crucial roll in achieving a successful implementation. For Co salicide, optimization of RTP conditions results in elimination of shallow junction leakage (its main scaling problem). Two-step RTP and one-step RTP Ti salicide processes are compared, showing the advantages of one-step RTP. The RTP process windows for low resistance narrow gates (the main scaling issue for Ti salicide) are analyzed. Processes with pre-amorphization, with Mo doping and with a combination of both are compared. An optimal process using Mo and preamorphization implants and one-step RTP is shown to result in excellent device characteristics and low resistance to 0.06 μm gates.

A model-based approach for process design and its application to the titanium salicide process

Process technology development constitutes a significant cost in manufacturing integrated circuits. In this paper, we present a model-based approach for developing new process technology rapidly and inexpensively, using the salicide process to demonstrate the concepts. This approach is applied to evaluate performance tradeoffs, to develop insight into the underlying process physics, to quantify the impact of the salicide process on the device and circuit performance, and to estimate the process variability. The key idea of this approach is to group a sequence of process steps into a process module, and build simple and accurate process models for the module. The paper also illustrates the use of this model-based approach in synthesizing optimal processes rapidly based on requirements, contributing to the reduction of technology development cost and cycle time.

A Simple Co Salicide Process Using Silicidation by N2/H2 RTA

ABSTRACTFor Co salicide process, a TiN cap layer is widely used to prevent oxidation of Co layers during silicidation by RTA. In this study, N2/H2 mixture ambient is used to eliminate the need for the TiN cap layer. The sheet resistance for the sample fabricated by N2 RTA without TiN cap layer shows large standard deviations for narrow N+ diffusion layers and shows 20% higher values and large standard deviations for P+ diffusion layers. On the other hand, the samples with N2/H2 RTA provides the same low and stable sheet resistance as those of the samples with TiN cap layer. XPS analysis shows that N2/H2 RTA suppresses oxidation of Co during the 1st RTA because of reduction by H2. B impurity in PMOS regions is known to retard silicidation of Co at 500°C. The retardation of silicidation seems to enhance oxidation of Co in PMOS regions by residual oxygen in the RTA chamber.

Silicide Technology in Deep Submicron Regime

ABSTRACTSilicide technology using cobalt-titanium alloy has been developed for sub-quarter micron devices. Extremely flat and epitaxial CoSi2 films are successfully grown on a (100) Si substrate. Improved SALICIDE process is not influenced by native oxide on a Si surface. This technology will be very useful in deep sub-quarter micron devices.