Ring Oscillator Research Articles

Role of temperature on linearity and analog/RF performance merits of a negative capacitance FinFET

Temperature plays a decisive role in semiconductor device performance and reliability analysis. The effect is more severe in a negative capacitance (NC) transistor, as the temperature modulates the ferroelectric polarization, implicitly included by the Landau coefficients (α, β, γ) in Technology Computer Aided Design (TCAD) simulations. In this paper, through TCAD simulations, the role of varying ambient temperature is investigated in the linearity and analog/radio-frequency (RF) merits of NC-FinFET. The varying temperature modulates the carrier mobility, the semiconductor bandgap, and the Landau parameter (α). We analyzed the analog/RF and linearity metrics, such as total gate capacitance (C gg), transconductance (g m), unity gain cut-off frequency (f T), the transconductance-frequency product, gain-bandwidth product, higher-order transconductance (g m2 and g m3), voltage intercept points, third-order power intercept and intermodulation points, and 1 dB CP using well-calibrated TCAD models. Our analysis reveals that these parameters are strongly dependent on temperature and the NC span (defined by using S-curve) shrinks with the rise in temperature. Finally, a source follower and three-stage ring oscillator are designed to test the frequency compatibility of the AC simulation for varying temperatures.

Creating and balancing the paths of arbiter-based physically unclonable functions on FPGA

Objectives. The problem of constructing a new structure of paths of physically unclonable function of the arbiter type (APUF) on the FPGA is being solved, based on the full use of internal resources of LUT-blocks, which are functionally repeaters. The relevance of the study is associated with the rapid development of physical cryptography tools. Another goal is the developing a methodology for eliminating the asymmetry of the APUF paths associated with the peculiarity of the synthesis of such circuits on the FPGA.Methods. The methods of synthesis of digital devices, their parametric modeling and implementation on rapid prototyping boards are used. A ring oscillator circuit is used to measure the internal propagation delays of signals through the APUF paths.Results. A new structure of the basic element of APUF paths with the use of two functional repeaters is proposed. The necessity of balancing the delays of APUF paths is demonstrated. A technique has been developed to eliminate the asymmetry of signal propagation through APUF paths based on controlled delay lines. The disadvantages of classical approaches as an APUF arbitrator and the need for their modification are shown.Conclusion. The proposed approach to build APUF paths has shown its viability and promise. An improvement in the characteristics of APUF constructed according to the proposed method, as well as a reduction in hardware costs during their implementation compared to classical APUF schemes, is experimentally confirmed. It seems promising to develop the described methodology for constructing the APUF to improve the structure of the arbiter.

Time- and Amplitude-Controlled Power Noise Generator against SPA Attacks for FPGA-Based IoT Devices

Power noise generation for masking power traces is a powerful countermeasure against Simple Power Analysis (SPA), and it has also been used against Differential Power Analysis (DPA) or Correlation Power Analysis (CPA) in the case of cryptographic circuits. This technique makes use of power consumption generators as basic modules, which are usually based on ring oscillators when implemented on FPGAs. These modules can be used to generate power noise and to also extract digital signatures through the power side channel for Intellectual Property (IP) protection purposes. In this paper, a new power consumption generator, named Xored High Consuming Module (XHCM), is proposed. XHCM improves, when compared to others proposals in the literature, the amount of current consumption per LUT when implemented on FPGAs. Experimental results show that these modules can achieve current increments in the range from 2.4 mA (with only 16 LUTs on Artix-7 devices with a power consumption density of 0.75 mW/LUT when using a single HCM) to 11.1 mA (with 67 LUTs when using 8 XHCMs, with a power consumption density of 0.83 mW/LUT). Moreover, a version controlled by Pulse-Width Modulation (PWM) has been developed, named PWM-XHCM, which is, as XHCM, suitable for power watermarking. In order to build countermeasures against SPA attacks, a multi-level XHCM (ML-XHCM) is also presented, which is capable of generating different power consumption levels with minimal area overhead (27 six-input LUTS for generating 16 different amplitude levels on Artix-7 devices). Finally, a randomized version, named RML-XHCM, has also been developed using two True Random Number Generators (TRNGs) to generate current consumption peaks with random amplitudes at random times. RML-XHCM requires less than 150 LUTs on Artix-7 devices. Taking into account these characteristics, two main contributions have been carried out in this article: first, XHCM and PWM-XHCM provide an efficient power consumption generator for extracting digital signatures through the power side channel, and on the other hand, ML-XHCM and RML-XHCM are powerful tools for the protection of processing units against SPA attacks in IoT devices implemented on FPGAs.

Design of ring oscillator with temperature compensation effect

In this article, a ring oscillator with Temperature Compensation Effect is proposed in 0.18 μm CMOS. The ring oscillator is composed of 31 stages of inverters in series. The change in ambient temperature will cause the oscillator frequency to deviate. Therefore, this research uses a voltage circuit with a positive temperature coefficient as the power supply for the oscillator circuit, so that the ring oscillator can output stable oscillation center frequency regardless of ambient temperature. The ring oscillator has been verified by simulation and experimental testing. The ambient temperature is within the range of −40°C to 80°C. The output frequency of the ring oscillator is stable at 33 kHz ± 0.50 kHz. The frequency error is within 1.6%. Temperature stability was 120 ppm/°C. At 1 MHz off the carrier, the phase noise is as low as −151.2 dBc/Hz and the total power dissipation is 210 μW. Compared with the previous scheme, the chip area and power consumption are lower. This circuit module can provide a clock signal for the timer when the UWB chip sleeps.

Measurement of Radiation Absorbed Dose Effects in SRAM-Based FPGAs

As of now, SRAM-based FPGAs are mainly preferred in the non-safety applications of NPPs. If the susceptibility to radiation effects of SRAM-FPGAs improves further, then the reliability of the applications can be improved. This experimental study investigates the radiation absorbed dose effects in SRAM-based FPGAs. The irradiation experiments have been conducted by keeping the device in both the power-on and power-off states inside a gamma radiation chamber of Co-60 source. In some applications, the device is deployed in the radiation environments and remains in the power-off condition for substantial period. At the time of need, the device may not function properly as demanded by the system due to the cumulative dose effect on SRAM-based FPGA. So the study of irradiation experiments on SRAM-FPGAs in the power-off state has its significant importance the same as the power-on state. The power supply current variation and the functionality failure of the device are monitored in both cases. In the power-on test, the device is configured with particular functionality and the parameters are measured continuously, but in the power-off test, the performance variations of the device are captured after configuring the device at particular time intervals during the course of the experiment. Along with the power supply current variation, we used an indirect method of measuring the propagation delay based on ring oscillator implementation. The device has been irradiated up to a dose level of 2.5 Mrad in power-on test and up to 50 Mrad in the power-off test.

Energy-Efficient Cyclic-Coupled Ring Oscillator With Delay-Based Injection Locking

This brief presents a new tristate-based delay cell to realize the recently proposed delay-based injection locking in ring oscillators. The circuit is then applied to implement a cyclic-coupled ring oscillator (CCRO). Compared to an inverter-based CCRO with multi-drive injection, the proposed circuit eliminates the static short-circuit current drawn from the supply when drive circuits are in conflicting logic states, thus reducing the power consumption of the CCRO. The functionality and improved energy efficiency of the proposed circuit is demonstrated with circuit simulations of a CCRO implemented in a 28-nm CMOS process. The CCRO employing the proposed technique achieves up to 25% lower power consumption and over 20% lower power-delay product (PDP) compared to the inverter-based CCRO.

Synergistic Effect of Multitone EMI on the Conducted Immunity of Integrated Oscillators

The performance of two oscillator circuits, namely a current-starved voltage controlled oscillator and a ring oscillator, is compared with respect to multi-tone direct power injection (DPI). The objective is to investigate the impact of causal dependence between multi-tones on the immunity levels of integrated blocks with different architectures but similar functionality. The multi-tone immunity analysis performed using the probabilistic noisy-OR model reveals an increase in the probability of failure due to electromagnetic interference relatively to single-tone EM disturbance. The proportions of inhibition and positive causality, as well as the mean degree of synergy ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DoS</i> ) caused by multi-tone EM disturbances, are extensively compared for both oscillator circuits.

Cylindrical Indentation to Selectively Stress Nanoscale CMOS Transistors

Advanced indentation techniques have been introduced to study the effects of multiple stresses on the transistor characteristics with using a cylindrical tip with various alignments. Particularly, controlling the cylinder tip orientation relative to the transistor channel direction is proposed to selectively strain the silicon channels in order to induce very different selectively controlled stresses. Several tip alignments allow to shift the stresses from uniaxial towards biaxial stress as well as to induce shear stress. Ring oscillator circuits based on NAND and NOR gates are used to monitor the stress effects on the characteristic circuit frequency as well as on the individual transistors. Finite Element simulations help to identify optimized setup properties for the targeted application. Comparison with previous indentation experiments derives the specific influence of each stress tensor component on the transistor characteristics.

A Programmable Multiple Frequencies Clock Generator With Process and Temperature Compensation Circuit for System on Chip Design

This article presents a programmable multiple frequencies clock generator with a process and temperature compensation circuit design. The proposed clock generator can achieve a stable and wide frequency range output for a single input frequency by using digital control codes as well as process and temperature compensation mechanisms. In our approach, the first step is to adjust the duty-cycle of the input clock by using a digitally controlled pulsewidth modulator (DCPWM) to generate an output clock signal with a duty-cycle of 20% to 80%. Second, the various duty-cycle clock outputs of the DCPWM are integrated by the duty-cycle-to-voltage converter to generate analog voltage signals to control the succeeding voltage-controlled ring oscillator (VCO). Through the use of various control voltages, different VCO output frequencies are generated. Finally, by using the process and temperature compensation circuit, the proposed clock generator can provide a stable and wide frequency range. The proposed chip is fabricated in a 180-nm CMOS process and has an output frequency range of 35–138 MHz at a supply voltage of 0.9 V. At 120 MHz, the power dissipation and rms jitter are 224.3 μW and 7.84 ps, respectively. The active area of the chip is 0.62 mm × 0.76 mm.

Time-domain Continuous-time Delta-sigma Modulator using VCO-based Integrator and GRO-based Quantizer

This paper presents a 3SUPrd/SUP-order time-domain continuous-time delta-sigma modulator (CTDSM) using two voltage-controlled oscillator (VCO)-based integrators and a gated ring oscillator (GRO)-based quantizer. The GRO-based quantizer has 1SUPst/SUP-order noise-shaping characteristics without the increase of the signal transfer function (STF) order and has magnificent linearity. Also, the output of the GRO-based quantizer has an intrinsic data weighted averaging (DWA)-based dynamic element matching (DEM) pattern that is less susceptible to the DAC mismatch. The PWM signal, which is the input of the GRO-based quantizer, is generated by the VCO-based integrator without additional blocks. In the pre-layout simulation, the CTDSM consumes 3.84 mW and achieves an SNDR of 71.2 dB at a 400-MSs sampling frequency and a 10-MHz bandwidth.

Ambipolar Organic Field‐Effect Transistors and Complementary Circuits Based on Single Crystals with Alcohol Treatment

AbstractAmbipolar organic field‐effect transistors (OFETs) are promising candidates for compact organic complementary circuits. High and balanced ambipolar mobilities that facilitate high operation speed and simplifying layout designs, as well as symmetric electrodes that minimize fabrication complexity are critical integrities for state‐of‐art ambipolar OFETs. Organic single crystals with intrinsic ambipolar characteristics are ideal active layer materials because of the high molecular ordering and low density of defects, whereas the generally low electron mobility hindered their further implantation. In this work, the highly crystallized 6,13‐bis(triisopropylsilylethynyl) pentacene single crystals are employed and successfully unveiled the intrinsic high electron mobility by a facile alcohol treatment approach. The resulting ambipolar OFETs showed averaged hole and electron mobilities both higher than 1 cm2 V−1 s−1 by a single type of metal electrode. The presented ambipolar OFETs not only improved the static and dynamic performance of ambipolar OFET‐based complementary inverters and ring oscillators by showing a high voltage gain of 186 and a short stage delay time of 0.7 ms, but they also allowed one logic gate to show two logic functions and potentially benefit the design and functionalities of future OFET‐based complementary circuits as well.

Alternate method to measure transmission and internal losses in non-planar ring oscillator laser

The transmission T and internal losses L of a non-planar ring oscillator (NPRO) laser are measured using a unique approach. Measurement of slope efficiency, axial mode separation, and relaxation oscillation frequency as a function of NPRO output power are all used in this procedure. T was assessed to be 2.3%, which was significantly higher than the supplier’s given value of 1.7% for a 32-deg angle of incidence at the NPRO output coupler at 1064 nm. The estimated value of internal loss was 4.2%.

CT PUF: Configurable Tristate PUF Against Machine Learning Attacks for IoT Security

Physical unclonable function (PUF) is a promising lightweight hardware security primitive for resource-limited Internet-of-Things (IoT) devices. Strong PUFs are suitable for lightweight device authentication because it can generate quantities of challenge-response pairs. Unfortunately, while the machine learning (ML) techniques have benefited various areas, such as Internet, industrial automation, robotics and gaming, they pose a severe threat to PUFs by easily modelling their behavior. This article first shows that even a recently reported dual-mode PUF can be cloned by ML (prediction accuracy of up to 95%). To solve this issue, we propose a configurable tristate (CT) PUF which can flexibly perform as an arbiter PUF, a ring oscillator (RO) PUF, or a bistable ring (BR) PUF with a bitwise XOR-based mechanism to obfuscate the relationship between the challenge and the response, hence resisting the ML attacks. An authentication protocol for the use in IoT security is presented. The CT PUF is implemented on Xilinx ZedBoard FPGAs with placement and routing details described. The experimental results show that the modelling accuracy of logistic regression (LR), support vector machine (SVM), covariance matrix adaptation evolutionary strategies (CMA-ES), and artificial neural network (ANN) is close to 60% (50% as the ideal number in theory) while meeting the PUF requirements for uniformity, reliability, and uniqueness. The hardware overhead and power consumption are slight. The entire project has been open sourced.

Patterning an Erosion-Free Polymeric Semiconductor Channel for Reliable All-Photolithography Organic Electronics.

Reliable patterning of organic semiconductors (OSCs) with high uniformity is essential to all-photolithography organic electronics. However, the majority of cross-linked OSCs experience performance fluctuations after photolithography because of the inherent vulnerability of low-ordered regions. Herein, we develop an anti-solution penetration photolithography process to achieve the reliable patterning of the OSC layer for all-photolithography integrated organic electronics. Using a thick and highly cross-linked semiconductor film and a low-solubility developer, an erosion-free semiconductor channel is obtained with a high mobility of up to 1.254 cm2 V-1 s-1 and a uniform threshold voltage close to zero. Compared with existing all-photolithography organic circuits, the unit logic gate area consumption is lower by 1-3 orders of magnitude at 0.0069 mm2, while the transistor density is higher by 1-2 orders of magnitude at 6780 Tr cm-2. The miniaturized organic inverters maintain uncompromised voltage gains, and the 15-stage organic ring oscillators feature higher oscillation frequencies, making them promising for applications in wide-ranging integrated organic circuits.

Inkjet‐Printed, Deep Subthreshold Operated Pseudo‐CMOS Inverters with High Voltage Gain and Low Power Consumption

AbstractOxide electronics has received increasing research and industrial attention in recent years. Solution‐processed/printed thin film transistors (TFTs) have rapidly matured to challenge its organic counterparts. However, when the n‐type oxides can demonstrate high mobility band transport, the performance of the p‐type ones is still weak. Consequently, examples of all‐oxide circuits are rare in the literature. Here printed amorphous indium‐gallium‐zinc oxide (a‐IGZO) based all‐oxide pseudo‐CMOS inverters, ring oscillators, and static random access memories (SRAMs), where the doping density and the device aspect ratio‐controlled deep‐subthreshold region offers sharp switching of the input signal is shown. For example, the signal gain (η) of pseudo‐CMOS 2T and 4T inverters is recorded as 285 and 329, respectively. Furthermore, the deep subthreshold operation ensures low dynamic power consumption, only few tens of nanowatts up to 1.5 V supply voltage. The inverters have demonstrated rail‐to‐rail swing up to 30 kHz and the 3‐stage ring oscillators recorded oscillation frequency of 6.7 kHz. The SRAM devices have shown satisfactory noise margins at HOLD‐, READ‐, and WRITE‐states, while their transient response is also recorded. These fully‐printed all‐oxide TFTs and circuits can be of large interest in portable/wearable electronics, display backplanes, interfacing circuits for sensors, etc.

Chain-Extending Polymerization for Significant Improvement in Organic Thin-Film Transistor Performance.

To achieve high-performance polymer semiconductors, it is crucially important to explore novel and effective synthesis strategies. Here, chain-extending polymerization as a synthesis strategy to design polymer semiconductors is introduced. Furthermore, we demonstrate its superiority over a conventional synthesis strategy─one-pot polymerization. Diketopyrrolopyrrole-thieno[3,2-b]thiophene-containing polymers (PDPPTT and PDPPTT-vinylene) are used in this study. PDPPTT and PDPPTT-vinylene are synthesized through one-pot polymerization and chain-extending polymerization, respectively. The utilization of this novel strategy enhances the hole/electron mobilities of PDPPTT-vinylene to up to 3.70/2.96 cm2 V-1 s-1 (compared to 2.71/0.63 cm2 V-1 s-1 for PDPPTT), thereby achieving the required performance for organic circuits like inverters and ring oscillators. The significant improvement in the transistor performance of PDPPTT-vinylene is attributed to the introduced vinylene linking units during the polymerization process, which can fine-tune the electronic structure, expand π-conjugation, and induce stronger intermolecular π-π interactions with more significant crystallization. These results demonstrate that chain-extending polymerization is an effective synthesis strategy for developing high-performance polymer semiconductors.

Analysis of Injection-Locked Ring Oscillators for Quadrature Clock Generation in Wireline or Optical Transceivers

Injection-locked ring oscillators (ILROs) are widely used for quadrature clock generators (QCG) in multi-lane wireline or optical transceivers because of their low power, low area, and technology scalability. However, locking a four-stage I/Q oscillator with a two-phase injection signal generates imbalances in amplitude and phase, resulting in I/Q phase errors and degraded jitter performance. This paper proposes a modified frequency-domain analysis with amplitude constraint for even-phase ILROs. Combining theoretical derivations with simulation results in 28nm CMOS technology, the behaviors of ring oscillators with partial injection and ILRO-based QCG are discussed and concluded.

Exploration and Device Optimization of Dielectric–Ferroelectric Sidewall Spacer in Negative Capacitance FinFET

Gate sidewall spacers, a pathway to the fringing fields, play a crucial role in the device design. In this article, using well-calibrated TCAD models, we have explored the impact of a sidewall ferroelectric (FE) spacer on a negative capacitance (NC) FinFET. In the proposed study, the FE layer is present beneath the gate electrode and at the spacer region that operates in the NC region. Through three novel FE–dielectric (FE–DE) spacer configurations, we found that proficient electrostatic control can be attained with the optimized stacked placement of the spacers. The fringing fields alter the FE polarization present at the spacer stack and modulates the channel charge, which is a prime objective of this work. Furthermore, we have varied the FE parameters, drain doping, and extension length to optimize the proposed FE–DE spacer configurations. We have done mixed-mode simulations to design an inverter and a three-stage ring oscillator to emphasize our results. The optimized spacer configuration shows~3.9% overshoot due to higher gate capacitance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{GG}$ </tex-math></inline-formula> ); however, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm{ON}} / I_{\mathrm{OFF}}$ </tex-math></inline-formula> ratio is approximately twic than that of the baseline counterpart. The results reveal that the optimized spacer configuration also mitigates the negative differential resistance (NDR), which allows the NC-based devices to be an efficient candidate for analog applications.

A High-Throughput Vernier Time-to-Digital Converter on FPGAs with Improved Resolution Using a Bi-Time Interpolation Scheme

A novel ring oscillator-based Vernier-type time interpolation method, known as the fine-timestamp maker, is proposed for field programmable gate array (FPGA)-based time-to-digital converters (TDCs). This method determines lower measurement dead time and improves resolution by using a bi-time interpolation scheme, first presented in this paper. Additionally, a group of cascaded delay units are packaged as an intellectual property core (DU-IP) to form a ring delay line and to adjust its length via the engineering change order (ECO) tool, which makes the adjustment of the ring oscillator’s frequency more linear and less position dependent. A prototype TDC was implemented on a Kintex-7 FPGA. The experimental results demonstrate that a single TDC channel only consumes 35 DFFs, 31 LUTs, and 16 CARRY4 logics after specific adjustment. The results, with a time resolution of 20 ps, dead time of 58 ns, and a root-mean-square error of 15–20 ps, show a significant performance improvement compared to traditional Vernier-type TDCs.

Polycrystalline InGaO Thin-Film Transistors with Coplanar Structure Exhibiting Average Mobility of ≈78 cm2 V-1 s-1 and Excellent Stability for Replacing Current Poly-Si Thin-Film Transistors for Organic Light-Emitting Diode Displays.

Highly ordered polycrystalline indium gallium oxide (PC-IGO) film is obtained by the crystallization of room temperature sputtered amorphous IGO on a hot plate at 350°C for 1 h and then annealed for 1 h in an N2 O environment. A high-density PC-IGO of ≈7.15g cm-3 with reduced oxygen vacancy (≈14.83%) and hydroxyl (OH) related defects (≈10.96%) has been obtained by N2 O annealing. Self-aligned coplanar thin-film transistor (TFT) with the PC-IGO exhibits the average saturation mobility of 78.73 cm2 V-1 s-1 , threshold voltage of -1.07V, subthreshold swing of 0.147V dec-1 , and the on/off current ratio of over 108 . The TFTs show excellent stability under bias-temperature stress with a negligible threshold voltage shift (ΔVTH ) of + 0.1 and -0.1V for the positive and negative bias stresses, respectively. The TFTs exhibit very stable environmental stability when the TFTs are stored under high humidity (85%) and a high temperature (85°C) for 2 days. The ring oscillator and the gate driver mode of the PC-IGO TFTs exhibit the propagation delay of 7.44ns/stage with rising/falling times of less than 0.7 μs, respectively. Therefore, the PC-IGO TFTs are suitable for large area, high-resolution active-matrix organic, and inorganic light-emitting diodes displays.