Ring Oscillator Research Articles

Spacer Engineering on Nanosheet FETs towards Device and Circuit Perspective

The Nanosheet FET (NS FET) has proven to be a potential candidate for sub-5-nm nodes. For the first time, in this manuscript, the NS FET performance is demonstrated by incorporating various device engineering at both device and circuit levels. Various device topologies like lightly doped drain/source, underlap, single and dual-k spacer are explored and the performance is compared with conventional NS FET. The NS FET with dual-k spacer is able to reduce the off current by 13.6× compared to the traditional NS FET. Further, the analog/RF figures of merit (FOMs) are assessed for various device configurations. Though the dual-k spacer outperforms in terms of DC and analog metrics, the conventional NS FET can offer better RF metrics owing to the high current. The crucial circuits for IC design such as inverter, ring oscillator, and common source (CS) amplifier are designed and evaluated the performance. The NS FET with dual-k spacer offers a gain of 1.815 for the CS amplifier and an oscillation frequency of 34.09 GHz for the 3-stage ring oscillator. The results will give insights into the performance of NS FET with various device architectures.

Oscillator Selection Strategies to Optimize a Physically Unclonable Function for IoT Systems Security.

Physically unclonable functions avoid storing secret information in non-volatile memories and only generate a key when it is necessary for an application, rising as a promising solution for the authentication of resource-constrained IoT devices. However, the need to minimize the predictability of physically unclonable functions is evident. The main purpose of this work is to determine the optimal way to construct a physically unclonable function. To do this, a ring oscillator physically unclonable function based on comparing oscillators in pairs has been implemented in an FPGA. This analysis shows that the frequencies of the oscillators greatly vary depending on their position in the FPGA, especially between oscillators implemented in different types of slices. Furthermore, the influence of the chosen locations of the ring oscillators on the quality of the physically unclonable function has been analyzed and we propose five strategies to select the locations of the oscillators. Among the strategies proposed, two of them stand out for their high uniqueness, reproducibility, and identifiability, so they can be used for authentication purposes. Finally, we have analyzed the reproducibility for the best strategy facing voltage and temperature variations, showing that it remains stable in the studied range.

Design of novel hybrid - digitally controlled oscillator for ADPLL

Digitally Controlled Oscillators (DCOs) are an integral part of All Digital Phase Locked Loops (ADPLLs). It is used to generate output frequency corresponding to the applied digital input. But, due to practical limitations in circuit design, DCOs resolution will be highly limited. Delta Sigma Modulator (DSM) is generally used in DCOs/ADPLLs to obtain a greater resolution. However, using DSM will lead to introduction of frequency spurs in the output spectrum. In this work we propose an alternate method to increase the frequency resolution of DCO without introducing frequency spurs. Novel Hybrid DCO architecture is proposed in this work to increase the resolution. Hybrid DCO proposed in this work has both digital and analog control for tuning frequency. Digital control input of the proposed DCO provides coarse frequency control and the analog control input provides fine frequency control. It has been demonstrated in this work that by integrating Hybrid DCO and DSM with an analog low pass filter (LPF), resolution can be greatly increased, without introducing spurs in the spectrum. As a proof of concept, two Hybrid Digitally controlled Ring Oscillators (DCROs) are designed in 90 nm CMOS process, and their period Jitter performance is compared.

Monolithic three‐dimensional integration of aligned carbon nanotube transistors for high‐performance integrated circuits

AbstractCarbon nanotube field‐effect transistors (CNT FETs) have been demonstrated to exhibit high performance only through low‐temperature fabrication process and require a low thermal budget to construct monolithic three‐dimensional (M3D) integrated circuits (ICs), which have been considered a promising technology to meet the demands of high‐bandwidth computing and fully functional integration. However, the lack of high‐quality CNT materials at the upper layer and a low‐parasitic interlayer dielectric (ILD) makes the reported M3D CNT FETs and ICs unable to provide the predicted high performance. In this work, we demonstrate a multilayer stackable process for M3D integration of high‐performance aligned carbon nanotube (A‐CNT) transistors and ICs. A low‐κ (~3) interlayer SiO2 layer is prepared from spin‐on‐glass (SOG) through processes with a highest temperature of 220°C, presenting low parasitic capacitance between two transistor layers and excellent planarization to offer an ideal surface for the A‐CNT and device fabrication process. A high‐quality A‐CNT film with a carrier mobility of 650 cm2 V–1 s–1 is prepared on the ILD layer through a clean transfer process, enabling the upper CNT FETs fabricated with a low‐temperature process to exhibit high on‐state current (1 mA μm–1) and peak transconductance (0.98 mS μm–1). The bottom A‐CNT FETs maintain pristine high performance after undergoing the ILD growth and upper FET fabrication. As a result, 5‐stage ring oscillators utilizing the M3D architecture show a gate propagation delay of 17 ps and an active region of approximately 100 μm2, representing the fastest and the most compact M3D ICs to date.image

High‐performance, coplanar amorphous InGaZnO thin‐film transistors by spray pyrolysis on polyimide substrate for low‐cost manufacturing of foldable active‐matrix organic light emitting diode display

AbstractWe report a method for low‐cost deposition of bubble‐free, high‐quality amorphous InGaZnO (a‐IGZO) on polyimide (PI) substrate for foldable active‐matrix organic light emitting diode (AMOLED) display by spray pyrolysis. The coplanar thin‐film transistor (TFT) with spray‐pyrolyzed (SP) a‐IGZO on PI substrate exhibits threshold voltage (VTH) of −0.8 V, saturation mobility of 40.95 cm2 V−1 s−1, and subthreshold swing of 0.18 V per decade with on/off drain current ratio of ~108. The high mobility TFT could be achieved using high substrate temperature (350°C) and low contact resistance by NF3 plasma on the SP a‐IGZO. The TFT shows a ΔVTH of −0.4 V when it is bent on a cylinder of 1‐mm radius. The TFT shows the ΔVTH of +0.05 V for positive bias temperature stress at +20 V at 60°C for 1 h. The ring oscillator made of a‐IGZO TFTs exhibits an oscillation frequency of 2.38 MHz at VDD of 10 V with a propagation delay of 9.13 ns per stage. Therefore, the a‐IGZO TFT by spray pyrolysis could be used for low‐cost, high‐performance, and flexible display TFT backplane.

A VCO-Based ADC With Direct Connection to a Microphone MEMS, 80-dB Peak SNDR and 438-μW Power Consumption

This article presents a microphone readout chip incorporating a voltage controlled oscillator (VCO)-based ADC that can be directly connected to a capacitive micro electro mechanical systems (MEMSs) sensor without requiring a voltage buffer. The ADC uses an open-loop pseudo-differential architecture with two ring oscillators followed by a coarse–fine frequency-to-digital converter. The proposed coarse–fine architecture optimizes power consumption, thanks to a new algorithm. The MEMS is connected to the ring oscillators with a source follower circuit that can be programed to interchange signal to noise ratio (SNR) by the power consumption in small steps. This feature enables always-on operation in voice recognition applications. The microphone is compatible with standard PDM audio interfaces. Total ADC power consumption ranges between 245 and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$438 \mu \text{W}$ </tex-math></inline-formula> for peak signal-to-noise and distortion ratios (SNDRs) between 74 and 80.3 dB-A, including the ADC and MEMS coupling circuitry. The dynamic range (DR) achieves 108 dB at full performance with a total harmonic distortion (THD) of 1.5% at the acoustic overload point (AOP) of 128 dBSPL. The ADC occupies an area of 0.14 mm2 implemented in 0.13- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS.

Dual-frequency fundamental-mode NPRO laser for low-noise microwave generation.

Monolithic nonplanar ring oscillators (NPROs) have achieved great success in industry, scientific applications and space missions due to their excellent narrow-linewidth, low-noise, high beam-quality, lightweight and compact performances. Here, we show that stable dual-frequency or multi-frequency fundamental-mode (DFFM or MFFM) laser can be stimulated directly by tunning pump divergence-angle and beam-waist injected to NPRO. The DFFM laser has a frequency deviation of one free spectral range of the resonator and thus can be utilized for pure microwave generation by common-mode-rejection. To demonstrate the purity of the microwave signal, a theoretical phase noise model is established, and the phase noise and the frequency tunability of the microwave signal are experimentally studied. Single sideband phase noise for a 5.7 GHz carrier is measured as low as -112 dBc/Hz at 10 kHz offset, and -150 dBc/Hz at 10 MHz offset in the free running condition of the laser, which outperforms its counterparts from dual-frequency Laguerre-Gaussian (LG) modes. The frequency of the microwave signal can be efficiently tunned through two channels, with frequency tunning coefficients of 15 Hz/V by piezo, and -60.5 kHz/K by temperature, respectively. We expect that such compact, tunable, low-cost and low-noise microwave sources can facilitate multiple applications including miniaturized atomic clocks, communication and radar, etc.

A Unified Multibit PUF and TRNG Based on Ring Oscillators for Secure IoT Devices

Physically Unclonable Functions (PUFs) and True Random Number Generators (TRNGs) are cryptographic primitives very well suited for secure IoT devices. This paper proposes a circuit, named multibit-RO-PUF-TRNG, which offers the advantages of unifying PUF and TRNG in the same design. It is based on counting the oscillations of pairs of ring oscillators (ROs), one of them acting as reference. Once the counter of the reference oscillator reaches a fixed value, the count value of the other RO is employed to provide the TRNG and the multibit PUF response. A mathematical model is presented that supports not only the circuit foundations but also a novel and simple calibration procedure that allows optimizing the selection of the design parameters. Experimental results are illustrated with large datasets from two families of FPGAs with different process nodes (90 nm and 28 nm). These results confirm that the proposed calibration provides TRNG and PUF responses with high quality. The raw TRNG bits do not need post-processing and the PUF bits (even 6 bits per RO) show very small aliasing. In the application context of obfuscating and reconstructing secrets generated by the TRNG, the multibit PUF response, together with the proposal of using error-correcting codes and RO selection adapted to each bit, provide savings of at least 79.38% of the ROs compared to using a unibit PUF without RO selection. The proposal has been implemented as an APB peripheral of a VexRiscv RV32I core to illustrate its use in a secure FPGA-based IoT device.

Total-Ionizing-Dose Effects on 3-D Sequentially Integrated FDSOI Ring Oscillators

Total-ionizing-dose responses are investigated for fully-depleted silicon-on-insulator (FDSOI) ring oscillators (RO), in three-dimensional (3D) architectures. Operational frequencies decrease after irradiation in these devices due primarily to threshold voltage shifts and transconductance degradation due to interface-trap buildup in the pull-up <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i> MOSFETs. 3D sequentially-integrated FDSOI ROs fabricated in the bottom layer of the 3D structure show the most significant frequency degradation. AC-bias irradiation leads to greater shifts than static-bias irradiation in these devices due to enhanced interface-trap buildup. Circuit simulations reinforce the relative importance of transconductance degradation in pull-up <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i> MOSFETs to the TID response of these ROs.

Neural Network-Based BSIM Transistor Model Framework: Currents, Charges, Variability, and Circuit Simulation

We present a neural network (NN)-based transistor modeling framework, which includes drain, source, and gate currents and charges and their variabilities. The training data are generated by a Berkeley short-channel IGFET model (BSIM) with ranges of channel lengths, widths, and oxide thicknesses. The NNs are trained to learn the geometry dependence. The drain, source, and gate currents are modeled with one NN and the charges by another NN. The NNs are trained to produce accurate variability prediction and derivatives of currents and charges. Quality and robustness tests, such as Gummel symmetry, harmonic balance, and ring oscillator, are performed and show excellent results.

Voltage controlled ring oscillator with large frequency range and variable duty cycle

Voltage controlled ring oscillator with large frequency range and variable duty cycle

Impact of Negative Capacitance Junctionless Nanowire (NCJLNW) MOSFET on Ring Oscillator Design and Analysis

This work presents the analysis of NCJLNW for low power analog/RF applications; this device shows reduced power consumption, reduced SCEs, smaller leakage and higher Ion/Ioff ratio. The results indicate that the proposed device improves the intrinsic gain, cut-off frequency, transconductance and reduces DIBL. The analysis of band-energy, surface-potential and electric-field has also shown promising results. Ring oscillator has been designed using this device; the analysis of the oscillator presents lower voltage of operation resulting into reduced power consumption, and high noise immunity. The frequency of oscillation is found to be higher at 172.1 GHz at a channel length of 20 nm.

Eternal-thing 2.0: Analog-Trojan-resilient Ripple-less Solar Harvesting System for Sustainable IoT

Recently, harvesting natural energy is gaining more attention than other conventional approaches for sustainable IoT. System on chip power requirement for the internet of things (IoT) and generating higher voltages on chip is a massive challenge for on-chip peripherals and systems. In this article, an on-chip reliable energy-harvesting system (EHS) is designed for IoT with an inductor-free methodology. The control section monitors the computational load and the recharging of the battery/super-capacitor. An efficient maximum power point tracking algorithm is also used to avoid quiescent power consumption. The reliability of the proposed EHS is improved by using an aging tolerant ring oscillator. The effect of Trojan on the performance of energy-harvesting system is analyzed, and proper detection and mitigation mechanism is proposed. Finally, the proposed ripple mitigation techniques further improves the performance of the aging sensor. The proposed EHS is designed and simulated in CMOS 90-nm technology. The output voltage is in the range of 3–3.55 V with an input 1–1.5 V with a power throughput of 0–22 μW. The EHS consumes power under the ultra-low-power requirements of IoT smart nodes.

Combined Random Number Generator on Programmable Logic Integrated Circuits

The paper shows the practical possibility of implementing random number generators on field programmable gate arrays (FPGA) by combining various physically unclonable functions. A compact and scalable scheme of a digital random number source based on an asynchronous flip-flop of the D-type is proposed, which combines the characteristics of a static memory physically unclonable functions and a ring oscillator physically unclonable functions. Unlike existing random number generators, the proposed scheme can be used to solve the problem of unclonable identification of digital devices. The article presents experimental results obtained by the proposed generator circuit based on the FPGA Xilinx Zynq. The main modes of operation, probabilistic and statistical characteristics of numerical sequences, generated by the proposed scheme are described.

NS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance

NanoSheet-Gate-All-Around-FETs (NS-GAAFETs) are commonly recognized as the future technology to push the digital node scaling into the sub-3 nm range. NS-GAAFETs are expected to replace FinFETs in a few years, as they provide highly electrostatic gate control thanks to the GAA structure, with four sides of the NS channel entirely enveloped by the gate. At the same time, the NS rectangular cross-section is demonstrated to be effective in its driving strength thanks to its high saturation current, tunable through the NS width used as a design parameter. In this work, we develop a NS-GAAFET compact model and we use it to link peculiar single-device parameters to digital circuit performance. In particular, we use the well-known BSIM-CMG core solver for multigate transistors as a starting point and develop an ad hoc resistive and capacitive network to model the NS-GAAFET geometrical and physical structure. Then, we employ the developed model to design and optimize a digital inverter and a five-stage ring oscillator, which we use as a performance benchmark for the NS-GAAFET technology. Through Cadence Virtuoso SPICE simulations, we investigate the digital NS-GAAFET performance for both high-performance and low-power nodes, according to the average future node present in the International Roadmap for Devices and Systems. We focus our analysis on the main different technological parameters with regard to FinFET, i.e., the inner and outer spacers. Our results highlight that in future technological nodes, the choice of alternative low-K dielectric materials for the NS spacers will assume increasing importance, being as relevant, or even more relevant, than photolithographic alignment and resolution at the sub-nm scale.

Highly reconfigurable oscillator-based Ising Machine through quasiperiodic modulation of coupling strength

Ising Machines (IMs) have the potential to outperform conventional Von-Neuman architectures in notoriously difficult optimization problems. Various IM implementations have been proposed based on quantum, optical, digital and analog CMOS, as well as emerging technologies. Networks of coupled electronic oscillators have recently been shown to exhibit characteristics required for implementing IMs. However, for this approach to successfully solve complex optimization problems, a highly reconfigurable implementation is needed. In this work, the possibility of implementing highly reconfigurable oscillator-based IMs is explored. An implementation based on quasiperiodically modulated coupling strength through a common medium is proposed and its potential is demonstrated through numerical simulations. Moreover, a proof-of-concept implementation based on CMOS coupled ring oscillators is proposed and its functionality is demonstrated. Simulation results show that our proposed architecture can consistently find the Max-Cut solution and demonstrate the potential to greatly simplify the physical implementation of highly reconfigurable oscillator-based IMs.

A true random number generator with high bit rate and low energy efficiency

SummaryIn this paper, a novel feedback architecture of true random number generator based on tetrahedral ring oscillator is proposed. The random raw bits are fed back to produce control voltages, which control the transmission gates in ring oscillators. Since random fluctuations of the control voltages increase the phase jitter of the oscillator, this architecture improves the bit rate and randomness of random sequence. Besides, a post‐processor is designed to enhance the randomness further. The circuit is implemented in TSMC 40‐nm complementary metal oxide semiconductor (CMOS) process, and it takes up an area of 85 × 51 μm. Measurement results show that the random number sequences pass the statistical randomness tests, with a low power consumption of 67 μW, high speed of 45 Mbps, and low energy efficiency of 1.48 pJ/bit.

Improving the Accuracy for Amplitude and Frequency of Analytical Equation of Single-ended Ring Oscillators Based on Circuit and Transistor Parameters

The analytical relationships presented for amplitude and frequency of the ring oscillator are derived approximately due to the nonlinear nature of this oscillator. In the case where the transistors experience the cut-off region, the relationships presented so far have no connection between the frequency and the dimensions of the transistor, which is not valid in practice. In this paper, considering the circuit’s governing equation and the ring oscillator’s output waveform, a relation for the frequency is presented, including the dimensions of the transistor. Also, a simple and approximately accurate relationship for the oscillator amplitude is provided in this case. The validity of these relationships has been investigated by analyzing and simulating a single-ended oscillator in 0.18μm technology.

A Closer Look at the Chaotic Ring Oscillators based TRNG Design

TRNG is an essential component for security applications. A vulnerable TRNG could be exploited to facilitate potential attacks or be related to a reduced key space, and eventually results in a compromised cryptographic system. A digital FIRO-/GARO-based TRNG with high throughput and high entropy rate was introduced by Jovan Dj. Golic (TC’06). However, the fact that periodic oscillation is a main failure of FIRO-/GARO-based TRNGs is noticed in the paper (Markus Dichtl, ePrint’15). We verify this problem and estimate the consequential entropy loss using Lyapunov exponents and the test suite of the NIST SP 800-90B standard. To address the problem of periodic oscillations, we propose several implementation guidelines based on a gate-level model, a design methodology to build a reliable GARO-based TRNG, and an online test to improve the robustness of FIRO-/GARO-based TRNGs. The gate-level implementation guidelines illustrate the causes of periodic oscillations, which are verified by actual implementation and bifurcation diagram. Based on the design methodology, a suitable feedback polynomial can be selected by evaluating the feedback polynomials. The analysis and understanding of periodic oscillation and FIRO-/GARO-based TRNGs are deepened by delay adjustment. A TRNG with the selected feedback polynomial may occasionally enter periodic oscillations, due to active attacks and the delay inconstancy of implementations. This inconstancy might be caused by self-heating, temperature and voltage fluctuation, and the process variation among different silicon chips. Thus, an online test module, as one indispensable component of TRNGs, is proposed to detect periodic oscillations. The detected periodic oscillation can be eliminated by adjusting feedback polynomial or delays to improve the robustness. The online test module is composed of a lightweight and responsive detector with a high detection rate, outperforming the existing detector design and statistical tests. The areas, power consumptions and frequencies are evaluated based on the ASIC implementations of a GARO, the sampling circuit and the online test module. The gate-level implementation guidelines promote the future establishment of the stochastic model of FIRO-/GARO-based TRNGs with a deeper understanding.

A Fault-Tolerant Current-Starved Ring Oscillator With Signal-Flip Protection Delay Cells Against Radiation Effects

This brief proposes a fault-tolerant current-starved ring oscillator to provide accurate clock signals against radiation effects. The ring oscillator adopts multiple signal-flip protection delay cells (SPDC) that can prevent unwanted signal flips due to external radiation. The SPDC utilizes input-dependent voltage limiters with delayed switching, maintaining the output voltage level against radiation effects, while minimally affecting normal operations of the delay cell. The proposed ring oscillator with SPDC was fabricated in 180-nm CMOS process and fully verified with chip tests in actual radiation environments. When generating 15 MHz clock signal at 1.8 V supply, the proposed ring oscillator ensures smaller frequency deviation from −5% to 11% with radiation charges of 0.25 pC compared to the conventional ring oscillator which suffers from large deviation from −35% to 79%. The minimum amount of radiation charge that causes >30% frequency deviation was 7.6x improved than conventional clock generators, verifying fault tolerance against large radiation effect.