Ring Oscillator Research Articles

Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET.

Single-port ferroelectric FET (FeFET) that performs write and read operations on the same electrical gate prevents its wide application in tunable analog electronics and suffers from read disturb, especially in the high-threshold voltage (VTH) state as the retention energy barrier is reduced by the applied read bias. To address both issues, we propose to adopt a read disturb-free dual-port FeFET where the write is performed on the gate featuring a ferroelectric layer and the read is done on a separate gate featuring a nonferroelectric dielectric. Combining the unique structure and the separate read gate, read disturb is eliminated as the applied field is aligned with polarization in the high-VTH state, thus improving its stability, while it is screened by the channel inversion charge and exerts no negative impact on the low-VTH state stability. Comprehensive theoretical and experimental validation has been performed on fully depleted silicon-on-insulator (FDSOI) FeFETs integrated on a 22 nm platform, which intrinsically has dual ports with its buried oxide layer acting as the nonferroelectric dielectric. Novel applications that can exploit the proposed dual-port FeFET are proposed and experimentally demonstrated for the first time, including FPGA that harnesses its read disturb-free feature and tunable analog electronics (e.g., frequency tunable ring oscillator in this work) leveraging the separated write and read paths.

Gate Stack Analysis of Nanosheet FET for Analog and Digital Circuit Applications

This manuscript demonstrates the performance comparison of vertically stacked nanosheet FET with various high-k materials in gate stack (GS) configuration. As the high-k dielectric materials are inevitable to continual scaling, in this paper, various high-k dielectric materials such as Si3N4, Al2O3 and HfO2 are incorporated in the GS, and the performance is studied. Further, DC and Analog/RF performance metrics are discussed in detail, and it is noticed that by using HfO2 in high-k GS, the on current (I ON) is enhanced by 46.7% and off current (I OFF) is decreased by 81.6% as compared to conventional NSFET (C-NSFET) without high-k GS. Also, the switching ratio (I ON/I OFF) is increased by 8× from SiO2 to HfO2, ensuring good logic applications. Moreover, compared to the C-NSFET, GS-NSFET with HfO2 offers better values for analog metrics like transconductance (gm) and transconductance generation factor (TGF). However, as the k value increases, the capacitances are also observed to be increased. As a result, the intrinsic delay (τ) increases by 9%, 6% and 20% from SiO2 to Si3N4, Si3N4 to Al2O3, Al2O3 to HfO2, respectively. On top of that, the circuit level demonstration is also performed for resistive load based inverter and ring oscillator (RO) for both C-NSFET GS NSFET with HfO2 as GS material. From circuit analysis, it is observed that by using the GS, the performance of the inverter is increased in terms of noise margins and DC gain. However, the oscillation frequency (f OSC) of 3-stage RO is decreased by 14.7% with the incorporation of GS owing to the increment in gate capacitance (Cgg). Consequently, the results will give deep insights into the performance analysis of NSFET with various high-k materials in gate stack at both device and circuit levels.

A lightweight true random number generator based on multi‐stage sampling the current starve based ring oscillator

AbstractIn this letter, a novel true random number generator (TRNG) with high energy‐efficient and throughput is proposed for cryptographic systems. The current starve based ring oscillator (CSRO) is biased in the subthrehold region as an entropy source. An individual ring oscillator (RO) is sampled using multiple sampling points of the CSRO working in the sub‐threshold region to obtain a multi‐channel sequence output, thereby fully exploiting the randomness of the entropy source. The proposed TRNG is implemented using a standard 40nm CMOS technology and the simulation results show that it provides high‐quality and 20.66 Mbps random sequences while only consuming 11.46 μW at 1.1 V, 25°C. In addition, the proposed TRNG passes the NIST SP 800‐22 and the NIST SP 800‐90B tests without post‐processing and outperforms the state‐of‐the‐art in terms of energy consumption per bit of the output bitstream, reaching 0.555pJ/bit.

A 0.004-mm2 3.65-mW 7-Bit 2-GS/s Single-Channel GRO-Based Time-Domain ADC Incorporating Dead-Zone Elimination and On-Chip Folding-Offset Calibration in 28-nm CMOS

This article reports an area-power-efficient 7-bit 2-GS/s time-domain analog-to-digital converter (TD-ADC) based on a gated ring oscillator (GRO). A pulse generator (PG) with the dead-zone elimination technique is devised for maximizing the linearity of the gated signal. The GRO-based time-to-digital converter employs a robust interpolation that effectively increases the interpolation accuracy of the GRO and improves the overall resolution. Also, a phase-tracking sampling generator is developed to suppress the leakage effect of the GRO and enhance the energy efficiency of the time-to-digital conversion. Moreover, a digital-assisted calibration technique is designed to eliminate the quantization error caused by the time-folding offset. The TD-ADC prototype is fabricated in a 28-nm CMOS process with an active area of 0.004 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> . It scores a measured peak SNDR of 38.63 dB and an SFDR of 50.66 dB at the conversion rate of 2 GS/s, along with the figure of merit (FoM) of 31.4 fJ/conversion step.

Discontinuity-Induced Bifurcations and Chaos in a Linear Ring Oscillator with a Piecewise Linear Reverse Coupling

Discontinuity-Induced Bifurcations and Chaos in a Linear Ring Oscillator with a Piecewise Linear Reverse Coupling

Monolithic VECSEL for stable kHz linewidth.

Vertical-external-cavity surface-emitting semiconductor lasers (VECSELs) are of increasing interest for applications requiring ultra-coherence and/or low noise at novel wavelengths; performance that is currently achieved via high-Q, air-spaced resonators to achieve long intra-cavity photon lifetimes (for the so-called class-A low noise regime), power scaling and high beam quality. Here, we report on the development of a compact, electronically tunable, monolithic-cavity, class-A VECSEL (monolithic VECSEL) for ultra-narrow free-running linewidths. A multi-quantum-well, resonant periodic gain structure with integrated distributed Bragg reflector (DBR) was optically-bonded to an air-gap-free laser resonator created inside a right-angle fused-silica prism to suppress the influence of environmental noise on the external laser oscillation, thus achieving high stability. Mode-hop-free wavelength tuning is performed via the stabilized temperature; or electronically, and with low latency, via a shear piezo-electric transducer mounted on the top of the prism. The free-running linewidth, estimated via the frequency power spectral density (PSD), is sub-kHz over ms timescales and <1.9 kHz for time sampling as long as 1s, demonstrating at least two orders-of-magnitude improvement in noise performance compared to previously reported single frequency VECSELs. The stable, total internal reflection resonator concept is akin to the prevalent monolithic non-planar ring oscillator (NPRO), however the monolithic VECSEL has several important advantages: tailored emission wavelength (via semiconductor bandgap engineering), no relaxation oscillations, no applied magnetic field, and low requirements on the pump beam quality. This approach is power-scalable in principle and could be applied to VECSELs at any of the wavelengths from the visible to the mid-infrared at which they are already available, to create a range of robust, ultra-coherent laser systems with reduced bulkiness and complexity. This is of particular interest for remote metrology and the translation of quantum technologies, such as optical clocks, from research laboratories into real world applications.

Ditch incorporated organic thin film transistor based organic all-p inverter: a novel approach

This paper demonstrates the static and dynamic characteristics of all-p organic inverter employing a bottom gate bottom contact organic thin film transistor with a ditch incorporated into the OSC and additional p+ doping done to its S/D nearing area. Various configurations of OTFT have been experimented with and it is found that as compared to an OTFT without extra p+ doping, the devices having additional doping show better responses. Where, for SG OTFT, ID is derived to be 18 μs, yet the one with extra doping illustrates a swooping 16.67% increased output current of 21 μs. To enhance the performance of the device further, a ditch of 30 nm, embedded 10 nm into the OSC is incorporated, further augmenting the performance of the device by 55.5% as compared to the conventional BGBC. Besides, the proposed inverter presents a considerably elevated performance in terms of robustness and low and high noise margins. This paper further compares the inverter using Diode Load Logic and Zero Vgs Load Logic topologies, wherein it was found that DLL shows an exceptional 211% less propagation delay τ p of 27 μs, as compared to 84 μs delay experienced by ZVLL. But comparing the two topologies in terms of the static response, ZVLL are way better and preferred over the counterparts since ZVLL configuration displays 20.5% augmented Noise Margin, improved gain, and overall robustness. Owing to the performance parameters achieved, such organic inverters may be incorporated into integrated circuits rendering trustworthiness to digital operations in electronic circuits and numerous cascading applications. Since the organic inverters made using the proposed OTFT exhibit a decent gain hence have an apparent prospective of driving myriad-stage logic like ring oscillators and memory blocks. Moreover, these may be employed in the areas of biosensors and wearable electronics as well wherever.

High power single-frequency 1112 nm laser by an insertable Nd:YAG/YAG bonded monolithic planar ring oscillator.

A high power single-frequency operation at 1112 nm with novel insertable monolithic planar ring oscillator based on a Nd:YAG/YAG bonded crystal is proposed. In a proof-of-principle experiment, a finely designed coating on the output surface is carried out to ensure single-wavelength oscillation at 1112 nm, together with a half-wave plate and a Tb3Ga5O12 crystal inserted in the open space of the bonded block to realize the unidirectional operation with power scalability. Consequently, the single-frequency laser delivers an output power of 3.9W at 1112.3 nm with a slope efficiency of 58.6% and an optical-to-optical efficiency of 17.7%. The power fluctuation is measured to be within ± 0.26% over 20 min, and the laser linewidth is estimated to be 4.15 MHz (Δλ = 0.017 pm).

Negative capacitance gate stack and Landau FET-based voltage amplifiers and circuits: Impact of ferroelectric thickness and domain variations

This article analyzes the impact of ferroelectric hafnium zirconium oxide (HZO) thickness (tFE) and domain number (N) variations on the negative capacitance (NC) effect in metal/HZO/metal gate stack and its implications on Landau FET-based device-circuit co-design through simulations. As tFE decreases, the NC effect weakens, resulting in less S-shaped hysteresis loops for charge and polarization versus voltage characteristics. The study highlights the trade-off between energy dissipation and NC effect voltage window in ferroelectric devices and the importance of balancing both. We developed Landau FET-based voltage amplifiers (VA), including passive VA (PVA) and active VA (AVA), and compared to existing counterparts such as P(VDF-TrFE)-PVA and PZT-AVA, across low and high frequencies. The proposed PVA shows a 22.60% and 54.31% increase in amplification (ANC) at low and high frequencies, respectively, compared to P(VDF-TrFE)-PVA. The AVA exhibits a 17.86% increase in ANC at low frequencies compared to PZT-AVA but no ANC at higher frequencies due to symmetry-breaking. The Landau FET-based inverter shows a sharp state transition than the CMOS inverter, but this sharpness depends on tFE, N, and the degree of NC effect. The Landau FET-based fan-out-4 inverter with 7.7 nm tFE and N = 16 is 25.49% faster than the Si MOSFET inverter. Moreover, the impact of tFE and N on the performance of the proposed 5-stage ring oscillator (RO) is investigated concerning state-of-the-art CMOS RO counterparts. The 5-stage RO using Landau FET-based inverters showed (1.26–18.9) times higher oscillation frequency (fOSC) and (17.93–5.71) times reduced power dissipation compared to the existing CMOS ROs. Finally, we examined how process variations impact the fOSC in the proposed 5-stage Landau FET-based RO. The findings indicate a standard deviation of 0.39 GHz in the distribution of fOSC. These findings highlight the interplay between tFE scaling, N variations, and transient NC effect, advancing Landau FET-based devices for future NC electronics.

SkyBridge 2.0: A Fine-grained Vertical 3D-IC Technology for Future ICs

Gate-all-around field effect transistors (FETs) are set to replace FinFETs to enable continued miniaturization of ICs in the deep nanometer regime. IMEC and IRDS roadmaps project that 3D integration of gate-all-around FETs is a key path for the IC industry beyond 2024. In this article, we present SkyBridge 2.0, an IC technology featuring high density fine-grained 3D integration of vertical gate-all-around nanowire FETs, contacts, and interconnect while also solving 3D routability. We utilize industry-standard EDA tools to develop a customized design and technology co-optimization (DTCO) flow to design and evaluate SkyBridge 2.0. This DTCO flow covers process emulation of standard cells and SRAM to enable scalable manufacturing pathway, TCAD characterization of vertical nanowire FETs to obtain IV and CV characteristics, compact modeling accurately the device behavior, RC parasitic extraction of 3D interconnects and performance, and power and area assessment using ring oscillators. The technology assessment using ring oscillators shows that SkyBridge 2.0 at the chosen design point, using 10 nm nanowires, achieves ∼18% performance and 31% energy efficiency benefits compared to 7 nm FinFET technology. Area analysis of logic cells shows up to six times density benefits versus aggressively scaled 2D-CMOS cells. In addition to logic, we architect 3D SRAM to support low-power memory designs. SkyBridge 2.0 SRAM shows ∼20% improvement in read and write static noise margin, up to three times lower leakage current, and up to four times density benefits compared to 7 nm FinFET technology.

Exploring the impact of domain numbers on negative capacitance effects in ferroelectric Device-Circuit Co-Design

This paper explores the performance of Hf0.5Zr0.5O2 (HZO)-stacked negative capacitance field-effect transistor (NCFET) for possible beyond complementary metal–oxide–semiconductor (CMOS) technology. For the first time, we investigate the impact of ferroelectric (FE) domain numbers on the negative capacitance (NC) effect, energy dissipation, NC effect voltage window, polarization ramping rate, voltage amplification (ANC), and oscillation frequency of a 5-stage HZO-NCFET inverter-based ring oscillator (HZO-NCFET-RO). The results show that HZO-NCFET is suitable for low-voltage and high-speed applications, providing a significant increase in ANC concerning the conventional PZT-NCFET and P(VDF-TrFE)-NCFET. Our study suggests that the HZO intrinsic NC effect time scale is tiny and limited by the FE switching. We show that the switching time of HZO is ∼20 times faster than the traditional FE [Pb(Nb0.04Zr0.28Ti0.68)O3]. Finally, the proposed 5-stage HZO-NCFET-RO offers superior performance with a 26% higher oscillation frequency and a 94.42% reduction in power dissipation compared to standard 5-stage CMOS inverter-based RO. These findings highlight the potential of HZO-stacked NCFET as an alternative device for the future beyond-CMOS technology.

Acousto-Optic Q-Switched Ho:YLF Ring Laser Based on Anti-Misalignment Resonant Cavity

An acousto-optic Q-switching Ho:YLF ring oscillator at 2066.33 nm with two anti-misalignment corner cube reflectors (CCRs) pumped by a 1940 nm thulium-doped fiber laser is demonstrated. The depolarization effect of the CCR is expressed in the form of equivalent transmission, and the transmission from two output directions of the oscillator is changing synchronously and periodically as the waveplate angle changes. In the experiment, under the pump power of 21.76 W, the optimum bidirectional energy of 3.13 mJ for a pulse duration of 122 ns at a repetition rate of 50 Hz is realized. The pulse energy reduction percentage at 50 Hz is 8% by changing the horizontal drift angle of one of the CCRs to 4.5°. The beam quality factor M2 is calculated to be about 1.10, revealing that the Ho laser is working in a fundamental transverse mode.

Prediction of variation aware FOSC in ring oscillators (ROs) to mitigate the impact of aging on RO-PUF

We propose a methodology to predict device-level variability (including aging) impact on the oscillation frequency (Fosc) of an N-stage ring oscillator (RO). This task is accomplished by creating a tool in a Python environment that uses our own developed variability-aware timing models of the CMOS inverter. Moreover, we use the model to foretell the impact of aging on the logical effort (g) of a CMOS inverter. Using the modified g, we resize ROs in an RO-based physical unclonable function (PUF) in the pre-layout stage to mitigate the impact of aging on the reliability of RO-PUF. The simulation is performed in the Cadence AMS environment using STMicroelectronics (STM) 28 nm CMOS process technology. With a one-time SPICE/aging simulation, the proposed methodology eliminates SPICE/aging simulation overhead for the prediction of variability impact on Fosc of a given N-stage RO. This approach mitigates the impact of aging on the reliability of RO-PUF and provides a method for variability (including aging) aware design in the pre-layout stage.

A 2.5 pJ/bit PVT-Tolerant True Random Number Generator Based on Native-NMOS-Regulated Ring Oscillator

In this brief, an energy-efficient true random number generator (TRNG) is presented based on the jitter noise of a single ring oscillator (RO). By XORing two different oscillation stages of the RO, consecutive pulses can be generated due to the fixed intrinsic propagation delay and more importantly, the time-varying jitter-noise-caused variation to the above delay. By continuously quantizing the above pulses’ width using another high-frequency RO-based time-to-digital converter (TDC), the TDC’s least significant bits (LSBs) are dominated by the jitter noise, of which the magnitude can be largely increased through reducing the RO’s supply voltage with a native NMOS transistor. Based on a 40-nm standard CMOS process, the proposed TRNG design is fabricated and extensively characterized. By passing the widely-exploited test tools of National Institute of Standards and Technology (NIST) and autocorrelation function, the proposed TRNG’s randomness has been well validated. Moreover, the randomness evaluation is further extended to various process-voltage-temperature (PVT) conditions, and the measured Shannon entropy is always larger than 0.999995, showing excellent PVT tolerance. Finally, the proposed TRNG features a high energy efficiency of 2.5 pJ/bit at a throughput of 53 Mbps.

FOM-CDS PUF: A Novel Configurable Dual State Strong PUF Based on Feedback Obfuscation Mechanism against Modeling Attacks

The configurable Ring oscillator Physical unclonable function (CRO PUF) is the newly proposed strong PUF based on classic RO PUF, which can generate exponential Challenge-Response Pairs (CRPs) and has good uniqueness and reliability. However, existing proposals have low hardware utilization and vulnerability to modeling attacks. In this paper, we propose a Novel Configurable Dual State (CDS) PUF with lower overhead and higher resistance to modeling attacks. This structure can be flexibly transformed into RO PUF and TERO PUF in the same topology according to the parity of the Hamming Weight (HW) of the challenge, which can achieve 100% utilization of the inverters and improve the efficiency of hardware utilization. A feedback obfuscation mechanism (FOM) is also proposed, which uses the stable count value of the ring oscillator in the PUF as the updated mask to confuse and hide the original challenge, significantly improving the effect of resisting modeling attacks. The proposed FOM-CDS PUF is analyzed by building a mathematical model and finally implemented on Xilinx Artix-7 FPGA, the test results show that the FOM-CDS PUF can effectively resist several popular modeling attack methods and the prediction accuracy is below 60%. Meanwhile it shows that the FOM-CDS PUF has good performance with uniformity, Bit Error Rate at different temperatures, Bit Error Rate at different voltages and uniqueness of 53.68%, 7.91%, 5.64% and 50.33% respectively.

Grazing, Homoclinic Orbits and Chaos in a Single-Loop Feedback System with a Discontinuous Function

Bifurcations and chaos of a three-dimensional single-loop feedback system with a discontinuous piecewise linear feedback function are examined. Chaotic attractors are generated at the same time of the destabilization of foci accompanied with grazing. Multiple periodic solutions are connected with homoclinic orbits based at a pseudo saddle-focus, which satisfies the condition of Shil’nikov chaos formally. The generation of chaotic oscillations is shown in a circuit experiment on a linear ring oscillator with a comparator. The homoclinic bifurcations and chaos are also shown in a ring neural network with a nonmonotonic neuron.

A 58-%-Lock-Range Divide-by-9 Injection-Locked Frequency Divider Using Harmonic-Control Technique

This paper presents a divide-by-9 injection-locked frequency divider (ILFD). It can lock onto about 6-GHz input with a locking range of 3.23 GHz (58%). The basic concept of the ILFD is based on employing self-gated multiple inputs into the multiple-stage ring oscillator. A wide lock range is also realized by adapting harmonic-control circuits, which can boost specific harmonics generated by mixing. The ILFD was fabricated using a 55-nm deeply depleted channel (DDC) CMOS process. It occupies an area of 0.0210mm2, and consumes a power of 14.4mW.

A Multilabel Active Learning Framework for Microcontroller Performance Screening

In safety-critical applications, microcontrollers have to be tested to satisfy strict quality and performances constraints. It has been demonstrated that on-chip ring oscillators can be used as speed monitors to reliably predict the performances. However, any machine-learning model is likely to be inaccurate if trained on an inadequate dataset, and labeling data for training is quite a costly process. In this paper, we present a methodology based on active learning to select the best samples to be included in the training set, significantly reducing the time and cost required. Moreover, since different speed measurements are available, we designed a multi-label technique to take advantage of their correlations. Experimental results demonstrate that the approach halves the training-set size, with respect to a random-labelling, while it increases the predictive accuracy, with respect to standard single-label machine-learning models.

CMOS backend-of-line compatible memory array and logic circuitries enabled by high performance atomic layer deposited ZnO thin-film transistor

The development of high-performance oxide-based transistors is critical to enable very large-scale integration (VLSI) of monolithic 3-D integrated circuit (IC) in complementary metal oxide semiconductor (CMOS) backend-of-line (BEOL). Atomic layer deposition (ALD) deposited ZnO is an attractive candidate due to its excellent electrical properties, low processing temperature below copper interconnect thermal budget, and conformal sidewall deposition for novel 3D architecture. An optimized ALD deposited ZnO thin-film transistor achieving a record field-effect and intrinsic mobility (µFE /µo) of 85/140 cm2/V·s is presented here. The ZnO TFT was integrated with HfO2 RRAM in a 1 kbit (32 × 32) 1T1R array, demonstrating functionalities in RRAM switching. In order to co-design for future technology requiring high performance BEOL circuitries implementation, a spice-compatible model of the ZnO TFTs was developed. We then present designs of various ZnO TFT-based inverters, and 5-stage ring oscillators through simulations and experiments with working frequency exceeding 10’s of MHz.

Analog and mixed circuit analysis of nanosheet FET at elevated temperatures

In this paper, for the first time, the performance of 3D Nanosheet FETs (NSFETs) is reported in the inversion (INV), accumulation (ACC), and junctionless (JL) modes at elevated temperatures. It is observed that, as the temperature increases from 25 °C to 200 °C, a decrement of 68% in mobility is observed for INV mode. In contrast, an increment of around 29% in mobility is observed for ACC and JL modes owing to the less scattering effects. Various crucial DC and analog/RF figures of merit (FOMs), such as SS, DIBL, gm, f T, etc, are assessed for different temperatures in all three modes. Further, the impact of temperature on circuit performance is demonstrated. From the circuit analyses, at 25 °C, an increment of around 12% in propagation delay is noticed for the JL and ACC mode inverter compared to the INV mode inverter due to higher I ON for INV mode. However, at 200 °C, JL inverter outperforms INV and ACC modes because of an increment in mobility. Moreover, for ring oscillator (RO), an oscillation frequency of 43.39 GHz, 38.9 GHz and 38.8 GHz for INV, ACC and JL mode ROs at 25 °C, whereas oscillation frequencies of 27.08 GHz, 39.2 GHz and 42.88 GHz are noticed for INV, ACC and JL mode ROs at 200 °C respectively. Though JL NSFET offers less intrinsic capacitances, at 25 °C, the frequency of oscillations (f osc) is high for INV mode because of higher I ON. Whereas, at 200 °C, the JL mode outperforms due to the absence of mobility degradation with temperature. These results will give an understanding of this future generation device at both device and circuit levels.