A 2.5 pJ/bit PVT-Tolerant True Random Number Generator Based on Native-NMOS-Regulated Ring Oscillator

Abstract

In this brief, an energy-efficient true random number generator (TRNG) is presented based on the jitter noise of a single ring oscillator (RO). By XORing two different oscillation stages of the RO, consecutive pulses can be generated due to the fixed intrinsic propagation delay and more importantly, the time-varying jitter-noise-caused variation to the above delay. By continuously quantizing the above pulses’ width using another high-frequency RO-based time-to-digital converter (TDC), the TDC’s least significant bits (LSBs) are dominated by the jitter noise, of which the magnitude can be largely increased through reducing the RO’s supply voltage with a native NMOS transistor. Based on a 40-nm standard CMOS process, the proposed TRNG design is fabricated and extensively characterized. By passing the widely-exploited test tools of National Institute of Standards and Technology (NIST) and autocorrelation function, the proposed TRNG’s randomness has been well validated. Moreover, the randomness evaluation is further extended to various process-voltage-temperature (PVT) conditions, and the measured Shannon entropy is always larger than 0.999995, showing excellent PVT tolerance. Finally, the proposed TRNG features a high energy efficiency of 2.5 pJ/bit at a throughput of 53 Mbps.