A 0.004-mm2 3.65-mW 7-Bit 2-GS/s Single-Channel GRO-Based Time-Domain ADC Incorporating Dead-Zone Elimination and On-Chip Folding-Offset Calibration in 28-nm CMOS

Abstract

This article reports an area-power-efficient 7-bit 2-GS/s time-domain analog-to-digital converter (TD-ADC) based on a gated ring oscillator (GRO). A pulse generator (PG) with the dead-zone elimination technique is devised for maximizing the linearity of the gated signal. The GRO-based time-to-digital converter employs a robust interpolation that effectively increases the interpolation accuracy of the GRO and improves the overall resolution. Also, a phase-tracking sampling generator is developed to suppress the leakage effect of the GRO and enhance the energy efficiency of the time-to-digital conversion. Moreover, a digital-assisted calibration technique is designed to eliminate the quantization error caused by the time-folding offset. The TD-ADC prototype is fabricated in a 28-nm CMOS process with an active area of 0.004 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> . It scores a measured peak SNDR of 38.63 dB and an SFDR of 50.66 dB at the conversion rate of 2 GS/s, along with the figure of merit (FoM) of 31.4 fJ/conversion step.