Ring Oscillator Research Articles

A 55 μ W 2.4 GHz wake-up receiver with offset-based peak detection achieving −90dBm sensitivity for IoT applications

The paper proposes a 2.4 GHz ultra-low power wake-up receiver (WuRX) with offset-based peak detection and mixer-first based radio frequency (RF) front-end for IoT applications. The mixer-first based front-end eliminates RF modules to reduce power consumption. Based on the transparency of the passive mixing switches, a 2-path passive mixer (2-PPM) constructs the high-Q band-pass filter (BPF) at the RF port to improve out-of-band blocker rejection. The offset-based peak detection circuit adaptively extracts the reference voltage for the subsequent comparator according to the real-time signal amplitude of envelope detection, which eliminates the misjudgment of the comparator and improves the accuracy of demodulation. For low power consumption, a ring oscillator is used to generate the local oscillator (LO) signal and the frequency calibration scheme combined with coarse tuning and fine tuning is employed to improve the frequency stability, which completes 10-bit frequency tuning with 2 MHz resolution. Designed in TSMC 28 nm CMOS technology, the mixer-first based front-end achieves a conversion gain of 42 dB and a noise figure of 11.9 dB at 2.4 GHz, an S11 less than −15dB during 2.4–2.5 GHz. The frequency calibration scheme for the ring oscillator completes the 512 MHz dynamic range with a 2 MHz frequency tuning step. The WuRX can achieve −90dBm sensitivity with 55 μ W power consumption at 0.6 V supply voltage and the chip area of 0.19 mm × 0.24 mm.

A dependable and resource-frugal ring oscillator physically unclonable function

ABSTRACT Silicon Physical Unclonable Function (PUF) is a crucial component for hardware security, providing unique device identification in networks. PUF provides robust security for cryptographic keys and IC digital fingerprints. However, resource constraints in network devices limit its use in security protocols. To address this challenge, PUF offers a lightweight hardware security solution with two main types: strong PUF (e.g. arbiter PUF) and Ring Oscillator (RO) PUF. The first option produces large CRPs with improved security but incurs hardware overhead, whereas the second option offers lower overhead with smaller CRP size, leading to reduced security. This paper introduces a novel, cost-effective solution to enhance RO PUF security while reducing hardware limitations. Our proposal involves a resource sharing technique with scan flip-flops, multiplexers, and inverter logic. This approach takes advantage of existing scan chains in circuit netlists to reduce PUF area without sacrificing uniqueness. A specific set of test patterns and odd number of inverters transform the memory-based PUF into an RO PUF. Our solution also leverages pass transistor-based implementation to significantly reduce power consumption and area overhead. Simulation results show that our approach effectively reduces area and power consumption while maintaining PUF uniqueness.

Flexible organic integrated circuits free of parasitic capacitance fabricated through a simple dual self‐alignment method

AbstractIn integrated circuits (ICs), the parasitic capacitance is one of the crucial factors that degrade the circuit dynamic performance; for instance, it reduces the operating frequency of the circuit. Eliminating the parasitic capacitance in organic transistors is notoriously challenging due to the inherent tradeoff between manufacturing costs and interlayer alignment accuracy. Here, we overcome such a limitation using a cost‐effective method for fabricating organic thin‐film transistors and rectifying diodes without redundant electrode overlaps. This is achieved by placing all electrodes horizontally and introducing sub‐100 nm gaps for separation. A representative small‐scale IC consisting of five‐stage ring oscillators based on the obtained nonparasitic transistors and diodes is fabricated on flexible substrates, which performs reliably at a low driving voltage of 1 V. Notably, the oscillator exhibits signal propagation delays of 5.8 μs per stage at a supply voltage of 20 V when utilizing pentacene as the active layer. Since parasitic capacitance has been a common challenge for all types of thin‐film transistors, our approach may pave the way toward the realization of flexible and large‐area ICs based on other emerging and highly performing semiconductors.

Design and Analysis of Ultra-low Power Voltage Controlled Oscillator in Nanoscale Technologies

In latest wired and wireless communication equipment, VCO (voltage-controlled oscillator) is the major building block and particularly used as the stable high frequency clock generator. VCO performance is measured through frequency range, power supply used, area occupied, power consumption, delay, and phase noise. VCO is the cascaded of odd number of inverter stages in a ring format, hence it is also articulated as a ring oscillator. Today’s portable communication devices are battery operated. Hence, low power and area efficient designs play a key role in battery life enhancement and device size reduction. Device scaling improves the effective silicon area utilization, but it leads to more leakages. Therefore, low power techniques along with the technology scaling is the best way of low power designs. In this article, discussed various low power schemes. The ring oscillator designs are carried out in various nano meter scaled technologies such as 180nm, 90nm,65nm and 45nm. A 5-stage ring oscillator is implemented in each technology along with low power schemes, simulated in Cadence virtuoso, and noted power, delay, and area. Observed that the proposed ring oscillator with sleepy keeper technique generated a stable frequency of oscillations in the range of 1GHz-2GHz. A control voltage of 1.8V to 0.4V is applied and targeted the power less than 30mW and delay in 0.25p sec.

Lightweight Strong PUF for Resource-Constrained Devices

Physical Unclonable Functions are security primitives that exploit the variation in integrated circuits’ manufacturing process, and, as a result, each instance processes applied stimuli differently. This feature can be used to provide a unique fingerprint of the electronic device, or as an interesting alternative to classic key storage methods. Due to their nature, they are often considered an element of the Internet of Things nodes. However, their application heavily depends on resource consumption. Lightweight architectures are proposed in the literature but are technology-dependent or still introduce significant hardware overhead. This paper presents a lightweight, Strong PUF based on ring oscillator architecture, which offers small hardware overhead and sufficient security levels for resource-constrained Internet of Things devices. The PUF design utilizes a Linear Feedback Shift Register-based scramble module to generate many challenge–response pairs from a small number of ring oscillators and a control module to manage the response generation process. The proposed PUF can be used as a Weak PUF for key generation or a Strong PUF for device authentication.

Multiphase injection locking for multiple rotary pulses in a coupled oscillator lattice loop

SummaryThis study provides design criteria of multiphase injection locking for an oscillator loop with multiple rotary pulses that can be utilized for an effective frequency multiplier. Coupled oscillator lattice loops can support phase waves. In the case where pulses rotate in the loop, the oscillatory signal exhibits times higher frequency than the rotation frequency of a single rotary pulse. Once an external signal succeeds in injection locking the single‐pulse rotation, the loop operates as an efficient times frequency multiplier. As in a ring oscillator, the progressive multiphase injection locking is best employed, when the loop supports only a single rotary pulse. Because the phase of the external signal becomes different for each pulse, progressive phase assignment does not work well for multiple rotary pulses; therefore, a more efficient scheme of phase assignment is investigated and validated by bifurcation analyses and measurements. The most effective multiphase injection locking is expected for the phase difference between two neighboring oscillators to be set to ( ), when pulses rotate to the cell address increases (decreases) in an oscillator loop.

Influence of the operating regime of the magnonic active ring oscillator on the performance of the magnonic reservoir computer based on it

A magnonic active ring oscillator based on an yttrium iron garnet (YIG) is a promising hardware platform for physical reservoir computing. It meets the required conditions for the availability of fading memory and nonlinearity. However, its performance still needs further improvement. Two methods can be employed to improve the performance. One is increasing the time of establishing steady self-oscillations in the auto-oscillator. The second one is increasing the amplitude of spin waves propagating in the YIG film. In this work, we achieve an increase of the amplitude of the reservoir response by broadening the available range for the ring gain coefficient. We use a metallized YIG film as a waveguide in which spin waves propagate. This shifts up the amplitude threshold for the development of spin wave modulation instability in the ring. The threshold defines the upper limit of the gain range for the ring. Binary pulse sequence is entered into the ring by switching its gain between upper and lower levels. The modulation instability threshold then sets the upper limit for the higher gain level. In addition, in this work, we set the lower level of the gain to negative values. This is one more improvement with respect to earlier works. Switching the gain between a negative and a positive value increases the amplitude of the reservoir response and the depth of its fading memory. We employ the standard short-term memory and parity-check tests to quantify the performance of the reservoir computer. Both tests demonstrate an increase in the computational efficiency of the magnonic reservoir.

Thermal and supply voltage analysis of optimized ring oscillator for pixel detector readout chip

This paper provides a specific study of the upgrade of the ATLAS pixel detector in preparation for the upgrade of the Large Hadron Collider (LHC). The upgrade to High Luminosity-LHC (HL-LHC) is expected to start after the long shutdown in 2025-2027. The scheduled upgrade for ATLAS will be able to efficiently cope with the challenges caused by the high luminosity imposed by the HL-LHC. A new full-silicon Detector Inner Tracker (ITk) will replace the current ATLAS Inner Detector (ID). The ITk pixel detector will consist of more layers than in the current pixel detector. This study focuses on the Ring Oscillator (ROSC) sensors embedded in the ITkPix-V1 Front-End chip of the ATLAS ITk pixel detector. The paper reports the frequency response of the ROSC at various temperatures and voltage supply values. The results showed a high sensitivity of ROSCs frequencies to the applied voltage and the external temperatures which indicates the reliability of the ITkPix-V1 chip for the future ITk pixel modules.

Printed organic transistors and complementary ring oscillators operatable at 200 mV

Applications of organic thin-film transistors (OTFTs) include wearable health monitors and next-generation Internet-of-Things systems driven by a small energy-harvesting power supply. Such applications require low voltage and low power consumption organic ICs. In this paper, we demonstrate complementary ICs based on printed p-type and n-type OTFTs operatable at an ultralow supply voltage of 200 mV. For that purpose, threshold voltages were finely tuned by dual-gate structure and self-assembled monolayer. Complementary inverter-based ring oscillators operated at small supply voltages down to 200 mV and exhibited a power consumption as small as 6 pW per stage.

An Optimized Temperature Compensated Ring Oscillator with Low Power Consumption and Low Variation

In this paper a low power ring oscillator with three differential delay stages and one output buffer stage is designed for Radio Frequency Identification (RFID) applications. The proposed oscillator is designed with neural network model and its parameters are optimized with Teaching–Learning Based Optimization (TLBO) algorithm. The central frequency of the oscillator becomes independent of the temperature with the help of two temperature compensation techniques. In the first technique, the PMOS load transistor of each stage is connected to the NMOS diode connected - in series - transistor. Since these two transistors work in complement of each other, the temperature variation of each stage’s output voltage is decreased. In the second technique, the current variation of oscillator stages versus temperature is reduced since the diode connected transistor is employed in the current source structure. The simulation is done in 0.18 µm Complementary Metal-Oxide Semiconductor (CMOS) technology with the help of Cadence software and the chip area of the layout designed with this software is 19×25 µm2. The designed oscillator exhibits the following parameters: a central frequency of 7.5 MHz, the power dissipation is 238 nW and the frequency deviation is 210 ppm/̊C in the temperature range of 0 to 120ºC, the noise phase and the period jitter are -87.05 dBc/Hz and 0.578 ns (rms), respectively, at 100 KHz offset frequency and 10000 clock cycle.

Design Guidelines and Feedback Structure of Ring Oscillator PUF for Performance Improvement

Design Guidelines and Feedback Structure of Ring Oscillator PUF for Performance Improvement

A 32-mV Supply Ring Oscillator Composed of Modified Schmitt Trigger Delay Cells for Integrated Start-up Circuits in DC Energy Harvesting Systems

A 32-mV Supply Ring Oscillator Composed of Modified Schmitt Trigger Delay Cells for Integrated Start-up Circuits in DC Energy Harvesting Systems

A Zero Trust-Based Framework Employing Blockchain Technology and Ring Oscillator Physical Unclonable Functions for Security of Field Programmable Gate Array Supply Chain

A Zero Trust-Based Framework Employing Blockchain Technology and Ring Oscillator Physical Unclonable Functions for Security of Field Programmable Gate Array Supply Chain

Strain tuning a Nonplanar Ring Oscillator by 3.5 GHz: Theory and Experiment

Strain tuning a Nonplanar Ring Oscillator by 3.5 GHz: Theory and Experiment

A Frequency Synthesizer With Automatic Frequency Calibration Robust to Initial Phase Error and Phase-Noise Enhanced Ring Oscillator

A Frequency Synthesizer With Automatic Frequency Calibration Robust to Initial Phase Error and Phase-Noise Enhanced Ring Oscillator

Jitter due to Random Telegraph Noise: a Study on the Time Dependent Variability of a Ring Oscillator

Random Telegraph Noise is a relevant source of variability in integrated circuits and a growing issue due to device scaling. Jitter is one of its consequences; therefore, it is an important parameter of performance measurements for electronic components and systems. In this paper, the relationship between Random Telegraph Noise and different concepts of jitter is studied. Firstly, a gate delay variability study of a CMOS inverter is discussed. Then, an absolute, a periodic, and a cycle-to-cycle jitter are evaluated in a five-stage ring oscillator. All the data were generated with a spice simulator modified to properly account for Random Telegraph Noise, using the Monte Carlo technique.

Battery-less luminance sensor biomimicking human sensory nervous system

With the evolution of materials science and microfabrication processes, energy harvesters have become sophisticated, achieving power outputs in the range of several milliwatts, and have become a promising alternative to conventional batteries. Although their output power is insufficient to continuously operate a wireless sensor module, energy harvesters can operate small integrated circuits, including timers, watches, and ring oscillators. In this study, we emulated the human sensory nervous system to develop a battery-less sensor with a built-in analog-to-digital converter. The human sensory nervous system comprises a sophisticated sensing mechanism that digitalizes external stimuli by pulse-density modulation. To mimic this behavior, we integrated a ring oscillator with photovoltaics, allowing it to function as a luminance sensor with an event-driven operation. The oscillation frequency of the ring oscillator changes with respect to the operating voltage; hence, the output voltage of the photovoltaic modulates the frequency by more than two orders of magnitude. The sensor exhibits oscillation frequencies of 10 kHz and 7.7 MHz corresponding to luminance levels of 25–25 000 lx. Its response times are 40 μs and 15 ms when the light source is turned on and off, respectively. Battery-less sensors expand the opportunities for the application of energy harvesters in biomedical, wearable, and environmental sensing.

A novel low hardware configurable ring oscillator (CRO) PUF for lightweight security applications

Physical unclonable function (PUF) is a promising hardware security primitive that can generate a unique secret key peculiar to each chip by extracting the differences of non-reproducible manufacturing variations for the same implementations. Although there are several types of PUF designs and structures, ring oscillator (RO) PUF is one of the most prominent PUFs due to its straightforward implementation and remarkable performance. However, the traditional RO-PUF does not support large sizes of input/output combinations or challenge-response pairs (CRPs), as it is called in the scope of PUFs. Consequently, RO-PUF is more vulnerable to adversary attacks which can reveal the PUFs’ CRPs using a machine learning approach. Increasing the size of RO-PUF's CRPs requires a high increase in the circuit size leading to unacceptable area overhead for lightweight applications. The primary technique used to increase RO-PUF CRPs’ size without increasing the size of the required hardware is to develop a configurable ring oscillator (CRO) PUF. In this paper, we propose a configurable logic unit (CLU) that can be utilized to build a low-hardware CRO-PUF. The proposed CLU consists of a 1-XOR gate and a 1-XNOR gate. Building a CRO-PUF using the proposed CLU dramatically increases the CRPs size while minimizing the required hardware. The proposed CRO-PUF achieves excellent evaluation results, with measured uniqueness of 50.1 %, uniformity of 49.45 %, and reliability of 98.33 %. These values are in close proximity to the ideal targets of 50 % for uniqueness and uniformity, and 100 % for reliability

Degradation Measurement and Modelling under Ageing in a 16 nm FinFET FPGA.

Most of the latest generation of integrated circuits use FinFET transistors for their performance, but what about their reliability? Does the architectural evolution from planar MOSFET to FinFET transistor have any effect on the integrated circuit reliability? In this article, we present a test bench we have developed to age and measure the degradation of 5103 ring oscillators (ROs) implemented in nine FPGAs with 16nm FinFET under different temperature and voltage conditions (Vnom≤Vstress≤1.3Vnom and 25°C≤Tstress≤115°C) close to operational conditions in order to predict reliability regarding degradation mechanisms at the transistor scale (BTI, HCI and TDDB) as realistically as possible. By comparing our initial RO measurements and the data extracted from Vivado, we will show that the performance of the nine FPGAs is between 50% and 70% of the best performance expected by Vivado. After 8000 h of ageing, we will see that the relative degradations of the RO are a maximum of 1%, which is a first indicator proving the FPGAs' good reliability. By comparing our results with similar studies on 28 nm MOSFET FPGAs, we will reveal that 16 nm FinFET FPGAs are more reliable. To be implemented in an FPGA, an RO uses logic resources (LUT) and routing resources. We will show that degradation in the two types of resources is different. For this reason, we will present a method for separating degradations in logical and routing resources based on RO degradation measures. Finally, we will model rising and falling edge propagation time degradations in an FPGA as a function of time, temperature, voltage, signal duty cycle and resources used in the FPGA.

Reliability analysis and comparison of ring-PUF based on probabilistic models

—To address the issue of maladaptive reliability theory models in delay-based physical unclonable functions (PUF) of ring classes, this paper begins by analyzing the relationship between four key transistor parameters (channel length, channel width, threshold voltage, and gate oxide thickness) and delay sensitivity. Then establishes reliability quantification formulas for various PUF types, including ring oscillator PUF, k-out-of-1 PUF, Loop PUF, transient effect ring oscillator PUF, and duty cycle PUF. This analysis and comparison are conducted using the inverter delay model and probabilistic statistical methods to ensure fairness at the theoretical level. Finally, the proposed model is validated through simulation experiments, along with further analysis and comparison of ring-PUF. The results demonstrate that delay sensitivity can be utilized to assess the extent of delay impact when process parameters fluctuate. In terms of reliability, the ring-PUF can be ranked as follows: k-out-of-1 PUF, Loop PUF, ring oscillator PUF, transient effect ring oscillator PUF, and duty cycle PUF. This paper offers extensive technical guidance and theoretical support for ring PUF designers.