Ring Oscillator Research Articles

Transit-time resonances enabling amplification and generation of terahertz radiation in periodic graphene p-i-n structures with the Zener–Klein interband tunneling

The Zener–Klein (ZK) interband tunneling in graphene layers (GLs) with the lateral n-i-n and p-i-n junctions results in the specific characteristics that can be used for the rectification, detection, amplification, and generation of the terahertz (THz) signals. The transit-time delay of the tunneling electrons and holes in the depletion regions leads to the phase shift between the THz current and THz voltage causing the negative dynamic conductance in a certain frequency range and resulting in the so-called transit-time (TT) instability. The combination of the ZK tunneling and the TT negative dynamic conductance enables resonant THz the amplification and generation of THz radiation. We propose the THz devices based on periodic cascade GL p-i-n structures exhibiting the TT resonances and evaluate their potential performance. Such structures can serve as THz amplifiers and, being placed in a Fabry–Pérot cavity, or coupled to a THz antenna or using a ring oscillator connection, as THz radiation sources.

Reconfigurable FET-Based Tunable Ring Oscillator and Its Single Event Effect Performance

In this work, reconfigurable Field Effect Transistor (RFET)-based ring oscillator (RO) has been proposed. RFET has two types of gates, control gate and program gate. This work investigates the possibility of exploiting the program gate of the RFET, for frequency tuning and duty cycle control using numerical device simulations. Different frequencies of operations have been demonstrated on the same oscillator by appropriately biasing the program gate. The program gates can also be used to control the duty cycle of the oscillator, at the given frequency. This paper also studies the single event effect (SEE) performance of the proposed RFET-RO. The simulation results suggest that the oscillators working at higher frequency are disturbed less compared to the oscillator working at lower frequency.

Carbon nanotube-based flexible high-speed circuits with sub-nanosecond stage delays

High-speed flexible circuits are required in flexible systems to realize real-time information analysis or to construct wireless communication modules for emerging applications. Here, we present scaled carbon nanotube-based thin film transistors (CNT-TFTs) with channel lengths down to 450 nm on 2-μm-thick parylene substrates, achieving state-of-the-art performances of high on-state current (187.6 μA μm−1) and large transconductance (123.3 μS μm−1). Scaling behavior analyses reveal that the enhanced performance introduced by scaling is attributed to channel resistance reduction while the contact resistance (180 ± 50 kΩ per tube) remains unchanged, which is comparable to that achieved in devices on rigid substrates, indicating great potential in ultimate scaled flexible CNT-TFTs with high performance comparable to their counterparts on rigid substrates where contact resistance dominates the performance. Five-stage flexible ring oscillators are built to benchmark the speed of scaled devices, demonstrating a 281 ps stage delay at a low supply voltage of 2.6 V.

A 3.2 GHz Injection-Locked Ring Oscillator-Based Phase-Locked-Loop for Clock Recovery

An injection-locked ring oscillator-based phase-locked-loop targeting clock recovery for space application at 3.2 GHz is presented here. Most clock recovery circuits need a very low phase noise and jitter performance and are thus based on LC-type oscillators. These excellent performances come at the expense of a very poor integration density. To alleviate this issue, this work introduces an injection-locked ring oscillator-based PLL circuit. The combination of the injection-locking process with the use of ring oscillators allows for the benefit of excellent jitter performance while presenting an extremely low surface area due to an architecture without any inductor. The injection locking principle is addressed, and evidence of its phase noise and jitter improvements are confirmed through measurement results. Indeed, phase noise and jitter enhancements up to 43 dB and 23.3 mUI, respectively, were measured. As intended, this work shows the best integration density compared to recent similar state-of-the-art studies. The whole architecture measures 0.1 mm2 while consuming 34.6 mW in a low-cost 180 nm CMOS technology.

Phase Noise Analysis of Separately Driven Ring Oscillators

In this paper, for the first time, the phase noise analysis of a Multi-loop Skew based Single Ended Oscillator (MSSROs) is derived and validated. Compared to the three stages of conventional ring oscillators (CROs), SDROs provide an equivalent oscillation frequency with improved phase noise with increasing stages. The primary distinction between these two designs (SDRO and three-stage CROs) is the inherent skew offset between the PMOS/NMOS gates caused by the unique connection. This skew offset is the fundamental cause of delay cell noise suppression; the SDROs have loosely coupled oscillators that run concurrently, forming multiple 3-stages of separately driven Ring Oscillators. As a result, a shaping function is derived in terms of skew offset, and simulating these with varying skew offset results in suppressing behavior. Additionally, we derived phase noise for a skew-based design and validated it in PDKs of 180nm and 65 nm. We plotted the thermal (flicker) noise contribution and found that increasing the number of stages leads to an approximately 1-2 dB reduction in phase noise while maintaining the same NMOS/PMOS size ratio. Finally, a 2-3 dB reduction in phase noise is achieved in MSSROs by incorporating the shaping function into phase noise equations.

ROPAD: Enhancing the Digital Ring Oscillator Probing Attempt Detector for Protecting Irregular Data Buses

Microprobing is applied to intercept data from on-chip signals, such as data passing through a data bus. Hence, it allows for extracting a full dump of this data, e.g., the firmware of a microcontroller, cryptographic key material, or any other type of passing data on the physical metal lines and/or the physical cells of the data bus connected to the metal lines. It is categorized as an invasive and physical attack vector against which software measures are insufficient for protection. As a countermeasure detecting microprobing attacks and enabling appropriate protection mechanisms, we propose a new probing detector for an industrial sub-40-nm advanced process node. It is based on ring oscillators (ROs), which are formed from the data bus lines. The oscillation frequency, caused by the capacity of bus lines, is measured and compared to detect any attached microprobes. The concept is optimized for detection of placed microprobes on both regular and irregular data buses or on any other pair of lines. For this purpose, a statistics-driven decision is made to distinguish probed from not probed lines. To improve the concept for high capacitance irregular lines, a hybrid design and test time calibration is proposed and analyzed, which shows the applicability of the concept under irregular bus lines, local variations, and jittery conditions. The results show that the approach results in low false positive (FP) and false negative (FN) rate at lower overhead comparing with alternative approaches.

GaN Ring Oscillators Operational at 500 °C Based on a GaN-on-Si Platform

A study of GaN for high temperature (HT, up to 500 °C) digital circuits was conducted. A HT-robust GaN-on-Si technology based on enhancement-mode p-GaN-gate AlGaN/GaN high electron mobility transistors (HEMTs) and depletion-mode AlGaN/GaN HEMTs was proposed and used to implement different digital circuit configurations, namely E/D-mode and E/E-mode (E: enhancement, D: depletion). The E/D-mode inverter was found to offer significantly better performance in terms of voltage swing, noise margin, and gain, across temperature and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\textit {DD}}$ </tex-math></inline-formula> scaling. As calculated from E/D-mode ring oscillators (ROs) with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{G}=2\,\,\mu \text{m}$ </tex-math></inline-formula> , a RO exhibited a propagation delay ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${t}_{p}$ </tex-math></inline-formula> ) of < 1.48 ns/stage at 500 °C. The best RO achieved <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${t}_{p} &lt; 0.18$ </tex-math></inline-formula> ns/stage at 25 °C. To the best of the authors’ knowledge, the proposed technology sets a new boundary of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${t}_{p}$ </tex-math></inline-formula> vs. <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{G}$ </tex-math></inline-formula> in wide band gap digital logic, and is operational at the highest reported temperature (500 °C) of a GaN digital circuit. The results reflect the promising potential of the proposed technology for emerging HT applications at 500 °C and beyond.

Design of Compensated Supply Circuit Topology for a Ring Oscillator

Design of Compensated Supply Circuit Topology for a Ring Oscillator

A comprehensive analysis and performance comparison of CombFET and NSFET for CMOS circuit applications

The performance of comb-like channel field effect transistor (CombFET) and nanosheet FET (NSFET) is addressed at both device and circuit levels at the 3-nm node. The CombFET is realized by combining both FinFET and NSFET structures in the channel area. At the device level, the DC, analog/RF figures of merit (FOMs) are analyzed in detail. From simulations, it is observed that the on current (ION) is enhanced by 42% from NSFET to CombFET at the same off current (IOFF) of 250 pA under the same footprint (FP). CombFET's improvement over NSFET is the result of the channel's wider effective width. Further, an improvement of 30% in cut-off frequency (fT) and a decrement of 20% in intrinsic delay (τ) is noticed from NSFET to CombFET. On top of that dimensional impact on the electrical performance of CombFET analysed in detail. The CMOS circuit behaviour for ring oscillator (RO) is studied using the Verilog-A model for both FETs in the CADENCE tool. An oscillation frequency (fOSC) of 111.9 GHz and 82.7 GHz was noticed for CombFET and NSFET, respectively. Thus, the analyses demonstrate that CombFET offers superior performance over NSFET without increasing the FP.

A temperature-insensitive process corner detection circuit based on self-timing ring oscillator

A process corner detection circuit based on a self-timing ring oscillator is proposed to identify on-chip process variations. Composed of a self-timing ring oscillator with 5 stages of C-element, a counting module and a reset module, it is able to distinguish slow, typical and fast dies. Implemented in a 40 nm CMOS process with 1.2 V supply and 100 MHz frequency, it has a small area of 436 μm2 with 0.18 mW power consumption. Implemented in the foundry's test circuit and tested with probe card in foundry, the measured results show that it can distinguish slow, typical and fast chips with no overlaps between the counting results under different temperatures of −25, 25, 75 and 125 °C. It is advantageous in its insensitivity to temperature for on-chip process corner detection.

An all-digital CMOS temperature sensor with a wide supply voltage range

This paper proposes a MOSFET-based all-digital temperature sensor fabricated in a standard 55-nm CMOS process. The temperature sensing elements of the sensor are composed of ring oscillators, which convert temperature information into frequency information. The frequency ratio’s proportional to absolute temperature (PTAT) feature is generated by using two separate frequency oscillators with varied temperature sensitivity. The frequency-to-digital converter (FDC) converts frequency information into digital representation without introducing any overhead reference clock. A die area of 1915µm2 is occupied, owing to the all-digital architecture. After two-point calibration, the proposed sensor achieves an error of -0.4°C∼+0.6°C throughout a temperature range of -40°C∼125°C. With the help of class-adjustable oscillators, the sensor can function in a wide supply voltage range from 0.5V to 1.2V. It obtains a resolution of 0.166°C at room temperature with a dissipation of 2.5µW.

Efficient RO-PUF for Generation of Identifiers and Keys in Resource-Constrained Embedded Systems

The generation of unique identifiers extracted from the physical characteristics of the underlying hardware ensures the protection of electronic devices against counterfeiting and provides security to the data they store and process. This work describes the design of an efficient Physical Unclonable Function (PUF) based on the differences in the frequency of Ring Oscillators (ROs) with identical layout due to variations in the technological processes involved in the manufacture of the integrated circuit. The logic resources available in the Xilinx Series-7 programmable devices are exploited in the design to make it more compact and achieve an optimal bit-per-area rate. On the other hand, the design parameters can also be adjusted to provide a high bit-per-time rate for a particular target device. The PUF has been encapsulated as a configurable Intellectual Property (IP) module, providing it with an AXI4-Lite interface to ease its incorporation into embedded systems in combination with soft- or hard-core implementations of general-purpose processors. The capability of the proposed RO-PUF to generate implementation-dependent identifiers has been extensively tested, using a series of metrics to evaluate its reliability and robustness for different configuration options. Finally, in order to demonstrate its utility to improve system security, the identifiers provided by RO-PUFs implemented on different devices have been used in a Helper Data Algorithm (HDA) to obfuscate and retrieve a secret key.

A PVT-Tolerant Oscillation-Collapse-Based True Random Number Generator With an Odd Number of Inverter Stages

This brief proposes a PVT-tolerant true random number generator (TRNG) based on a ring oscillator (RO) with an odd number of inverter stages. By introducing a Muller C-element in each racing path of the RO, the TRNG successfully eliminated the need of collapse detection circuits. The proposed topology enables a bidirectional controllability in the number of cycles to collapse (CTC) and provides flexibility for the number of random bits per cycle. Implemented TRNG in 40nm CMOS shows intrinsic robustness against PVT variations across a supply range of 0.5V-to-1.4V and a temperature range of −40°C-to-125°C without calibration. It consumes 0.0107 nJ/bit at 0.9V and occupies 305.6 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu {\mathrm{ m}}^{2}$ </tex-math></inline-formula> .

Electromagnetic Side-Channel Analysis Against TERO-Based TRNG

True random number generators (TRNGs) based on ring oscillators are employed in many devices because they can be constructed with logic gates only. Random numbers generated by TRNGs are used for various cryptographic systems as session keys, nonces, and masks. The randomness of a TRNG is characterized by uniformity, nonreproducibility, and unpredictability. Moreover, the quality of random numbers affects cryptographic systems. In particular, degradation of the unpredictability can reduce the security of the cryptographic system because random numbers can be easily estimated. Side-channel attacks, which exploit additional information leaked from a cryptographic module to reveal secret information, are well known. If some additional information reflecting the output bit can be measured from electromagnetic (EM) emission as a side-channel leakage against a TRNG, the unpredictability of the TRNG may decrease. Accordingly, this article introduces the leakage model that reflects an output bit generated by a transition effect ring oscillator (TERO) based TRNG, and an attack that estimates random number bits by measuring EM emission from an integrated circuit against TERO-based TRNG. We propose a leakage model against a TERO-based TRNG and demonstrate that the output bits of the TRNG can be estimated by analyzing the radiated emissions. We also consider a countermeasure against the proposed attack.

Systematic Design of Loop Circuit Topologies Using C/I DS Methodology

Herein, a systematic approach for designing loop topology circuits, such as ring oscillators (ROs), latches, and frequency dividers, is proposed. The design flow is devised to implement the target circuits with minimum power dissipation at the desired operating frequency. Using a modified <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C/I_{\text {DS}}$ </tex-math></inline-formula> methodology, several design examples in different technology nodes are provided showing less than ±5% error in the estimated circuit performance, confirmed by experimental data in 0.18 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mu }\text{m}$ </tex-math></inline-formula> technology. A standardized procedure has been developed to extract fundamental device characteristics for different technology nodes, which are subsequently fed into an optimizer script. Examples for implementing current-steering ROs and frequency dividers will be provided. The proposed approach can be employed to custom design high-speed sequential logic circuits, as well as voltage-controlled oscillators (VCOs), digitally controlled oscillators (DCOs), and frequency dividers for applications such as clock generators, sequential circuits, and serial data transceivers in modern integrated systems.

Spray Pyrolyzed Amorphous InGaZnO for High Performance, Self‐Aligned Coplanar Thin‐Film Transistor Backplanes

AbstractHigh‐performance, spray‐pyrolyzed amorphous indium‐gallium‐zinc oxide (a‐IGZO) thin‐film transistor (TFT) with self‐aligned (SA) coplanar structure is demonstrated. The spray‐pyrolyzed a‐IGZO film exhibits bubbles‐free smooth surface roughness (0.81 nm) and low oxygen‐related defects (22.5%). The fluorine‐doped a‐IGZO film shows a low resistivity of 1.18 × 10−3 Ω‐cm by NF3 plasma treatment. This is sufficient to obtain ohmic contact with the source/drain electrodes and doped IGZO in the offset region of the SA coplanar TFT. The spray‐pyrolyzed a‐IGZO TFT exhibits the field‐effect mobility (µFE) of 18.17 cm2 V−1 s−1, the threshold voltage (VTH) of −1.52 V, the subthreshold swing (SS) of 0.266 V dec−1, and a high on/off current ratio (Ion/Ioff) over 108 with a very low gate leakage current (&lt;10−13 A). The hysteresis‐free and highly stable performances are achieved due to the excellent a‐IGZO channel and SiO2 gate insulator interface. A twenty‐three‐stage ring oscillator is demonstrated with SA coplanar TFTs, exhibiting a high oscillation frequency of 2.66 MHz and a low propagation delay of 8.17 ns/stage. Therefore, the spray‐pyrolyzed a‐IGZO film can be a promising metal oxide semiconductor for high‐performance TFTs backplane in large areas and high‐resolution display applications.

Remaining useful life (RUL) regression using Long–Short Term Memory (LSTM) networks

The accurate prediction of the remaining useful life (RUL) of components is a major concern in electronic circuits. The RUL-based health diagnostics plays an important role in the determination of time-of-failure of a device as an early warning in industrial applications. In this paper, a Long Short Term Memory (LSTM) based regression model is proposed for the prediction of RUL of a Ring Oscillator (RO) circuit utilizing the most essential extracted electrical features of the device. LSTM networks are capable of capturing the temporal dependencies in the time-series data and eliminating the vanishing gradient problem encountered in the conventional recurrent neural networks (RNNs). From Cadence simulations, utilizing the 22 nm CMOS technology library, it has been demonstrated that the RO frequency degradation essentially depends on three major factors including the working temperature, voltage, and most importantly, the device aging parameter. The results show that more than 90% of the cases of the RUL prediction for the 13 and 21 stage constrained under the supply voltage variation from 0.7 V to 0.9 V with the least prediction deviation of 2 days to 6 days.

A Novel Bias Circuit Technique to Reduce the PVT Variation of the Ring Oscillator Frequency

Phase Locked Loop (PLL) is an on-chip clock generator for timing-centric electronic systems. Voltage Controlled Oscillator (VCO) is the key element for high-performance PLLs. A detailed qualitative explanation has been given to describe VCO operation. It is shown from simulation results that the variation of small signal transconductance ([Formula: see text]) is the main dominant source of frequency and gain ([Formula: see text]) variation in a VCO. In this work, simulation results for the conventional ring oscillator are presented which demonstrates [Formula: see text] times variation in [Formula: see text] across Process Voltage Temperature (PVT) corners. Such huge sensitivity to PVT is undesirable for high bandwidth PLL design. To mitigate this sensitivity, a constant-gm bias circuit is proposed in this paper, with a detailed mathematical analysis. A prototype of 4-stage ring oscillator with center frequency of 5[Formula: see text]GHz is developed in 65[Formula: see text]nm TSMC CMOS technology, and post-layout simulation results are carried out. Results show that maximum [Formula: see text] variation of 28% and frequency variation of 17% at a given control voltage. Temperature sensitivity has been decreased from 19.3% to 7% using the proposed biasing technique. Proposed solution consumes 2.4[Formula: see text]mW power from 1[Formula: see text]V power supply.

Development of a high accuracy and stability test bench for ageing measurement of 16 nm FinFETs based FPGA

This article describes the development of a test bench so as to measure the ageing of 16 nm FinFETs used in a Zynq UltraScale+ FPGA from Xilinx. The Ring Oscillator (RO) drift measurement method was chosen and implemented in the setup. However, RO is a circuit sensitive not only to ageing but also to temperature and voltage. In order to mitigate the undesired sensitivity to temperature and voltage, we installed a regulation system to control the temperature and the internal voltage of the FPGA, and we characterised the RO frequency in function of the temperature and the voltage to apply post-measurement compensations. We improved the measurement circuit by using the GPS signal as a time reference. 1000 h test with (TFPGA = 100∘C) and (VFPGA = Vnom + 25%) was performed and results show clear RO frequency drifts lower than 0.1 % measured with an accuracy of 0.9 × 10−4.

Numerical simulation of performance of magnonic reservoir computer based on active-ring oscillator

We carry out numerical simulation of the performance of a physical reservoir computer based on a magnonic active ring oscillator. Our numerical model is based on the theory of nonlinear spin-wave transient processes in magnetic films. We employ-two metrics to evaluate the performance, namely the short-term memory and parity-check capacities. Obtained results demonstrate that there exists high potential for improvement of performance characteristics of the reservoir computer. Finally, we formulate optimal physical parameters for the magnonic reservoir. Our numerical model shows that the optimized reservoir will be able to increase its short-term memory and parity check capacities by two times with respect to the experimentally demonstrated in recent papers.