Ring Oscillator Research Articles

Device and circuit-level performance comparison of GAA nanosheet FET with varied geometrical parameters

In this paper, DC and analog/RF figures of merit (FOMs) for different geometrical variations of the Gate all around (GAA) Nanosheet FET (NSFET) are computationally examined. For each nanosheet, the thickness (NT) varied from 5 nm to 9 nm and width (NW) varied from 10 nm to 50 nm to analyze the performance variations with the device's geometry. It is observed that DC metrics like switching ratio, drain induced barrier lowering (DIBL), and subthreshold swing (SS) degrade with increment in geometry of NS. Moreover, the increment in analog/RF FOMs like transconductance (gm), output conductance (gds), cutoff frequency (fT), transconductance frequency product (TFP), and gain bandwidth product (GBW) is observed as the width and thickness are increase towards 50 nm and 9 nm, respectively. However, intrinsic gain, GFP, and GTFP deteriorate as the physical dimensions of the NSFET increase. On top of that, inverter and ring oscillator (RO) circuits are designed and the performance is demonstrated by varying width of the nanosheet. The circuit analysis is performed in Cadence Virtuoso tool by using look-up table based Verilog-A model. A decrement of 17.6% in the delay of the inverter is noticed when the width is increased from 10 nm to 50 nm. Also, it is observed that the static current of inverter is less than pA, which ensures less static power dissipation. Furthermore, an increment of 46.5% in fosc of 3-stage RO is observed as width increased to 50 nm. According to the various results analyses, NSFET is a promising device for high performance and high frequency analog/RF applications for sub-7-nm technology nodes.

Perspective of 2D Integrated Electronic Circuits: Scientific Pipe Dream or Disruptive Technology?

Within the last decade, considerable efforts have been devoted to fabricating transistors utilizing 2D semiconductors. Also, small circuits consisting of a few transistors have been demonstrated, including inverters, ring oscillators, and static random access memory cells. However, for industrial applications, both time-zero and time-dependent variability in the performance of the transistors appear critical. While time-zero variability is primarily related to immature processing, time-dependent drifts are dominated by charge trapping at defects located at the channel/insulator interface and in the insulator itself, which can substantially degrade the stability of circuits. At the current state of the art, 2D transistors typically exhibit a few orders of magnitude higher trap densities than silicon devices, which considerably increases their time-dependent variability, resulting in stability and yield issues. Here, the stability of currently available 2D electronics is carefully evaluated using circuit simulations to determine the impact of transistor-related issues on the overall circuit performance. The results suggest that while the performance parameters of transistors based on certain material combinations are already getting close to being competitive with Si technologies, a reduction in variability and defect densities is required. Overall, the criteria for parameter variability serve as guidance for evaluating the future development of 2D technologies.

3–5 GHz FSK-OOK ultra wideband transmitter based on memristive ring oscillator

3–5 GHz FSK-OOK ultra wideband transmitter based on memristive ring oscillator

Low-Temperature (≤500 °C) Complementary Schottky Source/Drain FinFETs for 3D Sequential Integration.

In this work, low-temperature Schottky source/drain (S/D) MOSFETs are investigated as the top-tier devices for 3D sequential integration. Complementary Schottky S/D FinFETs are successfully fabricated with a maximum processing temperature of 500 °C. Through source/drain extension (SDE) engineering, competitive driving capability and switching properties are achieved in comparison to the conventional devices fabricated with a standard high-temperature (≥1000 °C) process flow. Schottky S/D PMOS exhibits an ON-state current (ION) of 76.07 μA/μm and ON-state to OFF-state current ratio (ION/IOFF) of 7 × 105, and those for NMOS are 48.57 μA/μm and 1 × 106. The CMOS inverter shows a voltage gain of 18V/V, a noise margin for high (NMH) of 0.17 V and for low (NML) of 0.43 V, with power consumption less than 0.9 μW at VDD of 0.8 V. Full functionality of CMOS ring oscillators (RO) are further demonstrated.

Closed vortex filament in a cylindrical domain: Circulation quantization

This article investigates quantum oscillations of a vortex ring with zero thickness that evolves in a cylindrical domain V=D×[0,L]. The symbol D denotes the planar domain, which is bounded by some closed connected curve S. The quantization scheme of this dynamical system is based on the approach proposed by the author earlier [“Small oscillations of a vortex ring: Hamiltonian formalism and quantization,” Eur. J. Mech. B/Fluids 92, 100–106 (2022); arXiv:Math-ph/2112.04859v1]. As result, we find the discrete values Γn for circulation Γ. In contrast to the traditional approach where such quantities are usually postulated, the values Γn are deduced rigorously as the consequence of the conventional scheme of quantum theory. The model demonstrates the splitting of levels also. In particular, the levels correction values depend on the domain V: both the cylinder height L and the form of the curve S affect the final formula for the quantities Γn. Moreover, we prove that the basic circulation levels demonstrate a “fine structure.” These anomalous terms, which are proportional to the value ℏ2, are calculated in the article as well. The conclusions are compared with some results of numerical simulations by other authors “Intermittency of velocity circulation in quantum turbulence,” Phys. Rev. X 11, 011053 (2021).

Prime factorization using coupled oscillators with positive feedback

Prime factorization is a procedure of determining the prime factors of a given number N that requires super-polynomial time for conventional digital computers. In this work, we describe an approach to prime factorization using coupled oscillators with positive feedback. The approach includes several steps, where some of the steps are accomplished on a general type computer, and some steps are accomplished using coupled oscillators. We present experimental data on finding the primes of N = 817. The experiment is performed on a system of two coupled active ring oscillators. Each of the oscillators possesses its own set of eigenfrequencies that can be independently controlled by the external phase shifter. The coupling allows us to check on any common frequency that leads to the phase lock-in and power increase in the circuit. One of the ring oscillators includes a spin wave magnetic delay line made of Y3Fe2(FeO4)3, while the second oscillator includes an ordinary coaxial cable as a delay line. There are 22 eigenfrequencies for the spin wave oscillator and 4 eigenfrequencies for the oscillator with coaxial cable in the frequency band of operation. It takes less than 10 μs for the system to find the common frequency (if any). The most appealing property of the proposed circuit is that the processing time does not scale with the number of eigenfrequencies. Potentially, circuits with coupled active ring oscillators can be utilized to solve a variety of computational problems.

Temperature compensated ring oscillator based VCO

Frequency drift due to temperature variations is a crucial design consideration and cannot always be compensated by a phase-locked loop especially when low-gain, multiband oscillators are employed. A ring oscillator architecture with reduced frequency drift over temperature is presented in this paper. The oscillator is incorporated in a phase locked loop (PLL) to produce a stable clock within the required frequency range under process, voltage, and temperature variations. The output frequency of the oscillator is compensated through a proportional to absolute temperature (PTAT) current in order to eliminate the frequency drift. A proof-of-concept PLL has been designed and fabricated in a 180 nm CMOS technology operating with 3.3 V supply voltage and providing a 480 MHz frequency. Measurement results of the fabricated chip show a frequency variation of the VCO from −1.5 % to + 0.4 % from the center frequency across the temperature range from −40 °C to 120 °C meeting the requirements for most consumer market applications. The duty cycle distortion is less than 1% across the temperature range. The phase noise of the oscillator was measured at −107 dBc/Hz.

Unsupervised recycled FPGA detection using exhaustive nearest neighbor residual analysis

Measuring and analyzing aging-induced delay degradation of ring oscillators (ROs) is an effective method to detect recycled field-programmable gate arrays (FPGAs). However, detection methods of conventional recycled FPGAs detection methods assume the existence of known fresh FPGAs (KFFs) as training data for machine-learning-based classification, which is an unrealistic assumption. In this paper, we propose an unsupervised recycled FPGA detection method, where little information on KFF is available. In the proposed method, estimated frequency is calculated from neighboring ROs, and then the residual frequency between the measured and estimated frequencies is used for the detection. Because of the systematic component of process variation, the frequencies of neighboring ROs should be similar when the target FPGA is fresh. Therefore, if the residual is high, the target FPGA is determined as recycled. Experiments using 25 commercial FPGAs under various aging scenarios demonstrate that the proposed method successfully distinguishes between recycled and fresh FPGAs.

Implementation of TRNG with SHA-3 for hardware security

Random Number Generators (RNGs) are the solution for cryptographic applications to enhance hardware security. These RNGs ought to have three specific properties unpredictability, aperiodic, and good statistical criteria. This brief presents a True Random Number Generator (TRNG) based on Ring oscillators' jitter with MLFSR. The MLFSR is augmented with a set of prime primitive polynomials, Boolean, and non-linear functions to attain a non-linear, unpredictable, and extended sequence period. Paper mainly focused on achieving high randomness by integrated the TRNG with a new promising crypto engine Keccak as a post-processing block; leads to extensively more security in data transfer, encryption keys, data authenticity of ICs, and IoT based applications. The RNG design is coded in Verilog HDL and implemented on the FPGA Zed board. Hashing is performed with a throughput of 2.4Gbps at 100 MHz either with RNG data or SHA data. Evaluated the randomness of the generated non-deterministic bitstreams (10 Mb) using the NIST 800–22 & Diehard test suite and successfully passed.

A 0.5 V Sub-Threshold CMOS Current-Controlled Ring Oscillator for IoT and Implantable Devices

A current-controlled CMOS ring oscillator topology, which exploits the bulk voltages of the inverter stages as control terminals to tune the oscillation frequency, is proposed and analyzed. The solution can be adopted in sub-1 V applications, as it exploits MOSFETS in the subthreshold regime. Oscillators made up of 3, 5, and 7 stages designed in a standard 28-nm technology and supplied by 0.5 V, were simulated. By exploiting a programmable capacitor array, it allows a very large range of oscillation frequencies to be set, from 1 MHz to about 1 GHz, with a limited current consumption. Considering, for example, the five-stage topology, a nominal oscillation frequency of 516 MHz is obtained with an average power dissipation of about 29 µW. The solution provides a tuneable oscillation frequency, which can be adjusted from 360 to 640 MHz by controlling the bias current with a sensitivity of 0.43 MHz/nA.

A novel approach for designing of variability aware low‐power logic gates

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are continuously scaling down in the nanoscale region to improve the functionality of integrated circuits. The scaling down of MOSFET devices causes short-channel effects in the nanoscale region. In nanoscale region, leakage current components are increasing, resulting in substantial power dissipation. Very large-scale integration designers are constantly exploring different effective methods of mitigating the power dissipation. In this study, a transistor-level input-controlled stacking (ICS) approach is proposed for minimizing significant power dissipation. A low-power ICS approach is extensively discussed to verify its importance in low-power applications. Circuit reliability is monitored for process and voltage and temperature variations. The ICS approach is designed and simulated using Cadence's tools and compared with existing low-power and high-speed techniques at a 22-nm technology node. The ICS approach decreases power dissipation by 84.95% at a cost of 5.89 times increase in propagation delay, and improves energy dissipation reliability by 82.54% compared with conventional circuit for a ring oscillator comprising 5-inverters.

Design of True Random Number Generator Based on Multi-Stage Feedback Ring Oscillator

True random number generators (TRNGs) play an important role in encryption systems. In this brief, a novel method of generating true random numbers on a field-programmable gate array (FPGA) is proposed based on the random jitter of a multi-stage feedback ring oscillator (MSFRO) as the entropy source. Based on the traditional ring oscillator, a multi-stage feedback structure is added to enlarge the range of clock jitter, and improve the frequency of clock sampling and the randomness of the entropy source. Different from the traditional clock sampling structure, we use the clock jitter signal generated by the MSFRO to sample the clock signal generated by the phase-locked loop (PLL) of the FPGA. The obtained output value is operated by XOR to reduce the deviation of the output value and improve its randomness. The TRNG is implemented in Xilinx Virtex-6 FPGA, which has low hardware resource consumption and high throughput. The entropy source classification, hardware resources and throughput are compared with those of existing TRNGs. The results showed that the proposed TRNG only consumed 24 LUTs and 2 DFFs. Compared with other TRNGs, this design has very low hardware resource consumption and its throughput is up to 290 Mbps. The random bit sequence generated by this TRNG passes the NIST SP800-22 test and the NIST SP800-90B test.

Integrated Circuit Authentication Based on Resistor and Capacitor Variations of a Low Pass Filter (LoPUF)

Because of chip fabrication outsourcing, piracy, reverse engineering, and counterfeiting are major concerns for the semiconductor industry as well as the government. To prevent these issues, Physical Unclonable Functions (PUFs) based methods have been proposed has a way to authenticate chips. PUFs extract randomness from the manufacturing variations of a device that is probabilistic in nature. PUFs are generally easy to implement, but, because of its random behavior, its response is hard to predict and model. Many existing PUF techniques such as arbiter and ring oscillator can be hard to implement inside a chip because of their large area overhead. Hence, we have proposed a novel low pass filter PUF design in this work based on the internal resistor and capacitor variations within an IC. We have simulated the setup in Cadence Virtuoso for a 45 nm technology node. The resultant output voltage of our proposed PUF will be different at the same cut-off frequency because of the manufacturing variations. Finally, the output of the low pass filter PUF is connected with an inverter to make the signal digital and after that, a digital counter is connected with the inverter to measure the pulse width that can be used for generating a unique PUF output.

Methodology for Readout and Ring Oscillator Optimization Toward Energy-Efficient VCO-Based ADCs

For the design of ring oscillator-based ADCs, little has been reported on how to optimally co-design the readout scheme and the ring oscillator core towards optimal energy efficiency. This paper describes a methodology to find this optimum for a target SQNR and signal bandwidth, for the case of 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> -order quantization noise shaping. In short, starting from initial assumptions on the VCO, the readout optimization boils down to finding the best VCO frequency. From this, the number of readout phases, the sampling frequency of the readout and the number of bits in the quantizers are derived. Then, it is explained how to adjust the VCO core toward the corresponding optimal VCO configuration. This is discussed for the case of a current-controlled ring oscillator, indicating the main constraints that define the design space for such a VCO optimization. If the actual VCO configuration is bounded by practical constraints, this approach can be re-iterated where a new readout optimization is performed taking these constraints into account.

Effect of Frequency on Total Ionizing Dose Response of Ring Oscillator Circuits at the 7-nm Bulk FinFET Node

Total ionizing dose (TID) effects at the 7-nm bulk FinFET node are characterized under dynamic and static test conditions through changes in ring oscillator (RO) frequencies, leakage currents, and inverter delays. Results from total-dose exposures using the ARACOR X-ray machine showed that static conditions represented the worst case conditions. Higher operating frequencies resulted in increased leakage currents and inverter delays after irradiation. The rate of change for leakage current was inversely proportional to frequency during exposure. The rate of change for inverter delay was directly related to frequency during TID exposure. Overall, degradations in circuit-level parameters (logic gate delays and operating current) were less than 1% for TID exposures of 435 krad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ).

A 3.2-GHz 405 fsrms Jitter –237.2 dB FoMJIT Ring-Based Fractional-N Synthesizer

A ring-oscillator (RO)-based low-jitter digital fractional-N frequency synthesizer is presented. It employs a frequency doubler (FD) that doubles the reference clock frequency, a 2-bit time-to-digital converter (TDC) with optimized thresholds to minimize the quantization error, and a high-resolution digital-to-time converter (DTC) to cancel the quantization error of the delta-sigma fractional divider (FDIV). DTC’s linearity is improved using a piecewise linear (PWL) function-based correction scheme. On-chip digital calibration is extensively used to correct imperfections of the FD, TDC, and DTC. A prototype synthesizer incorporating the proposed techniques and implemented in a 65-nm CMOS produces a 3.2-GHz output clock from a 96-MHz input clock. The worst-case integrated jitter is 306 and 405 fs in integer and fractional-N modes, respectively. The synthesizer consumes 11.7 mW from a 1-V supply of which 7.84 mW is consumed by the oscillator. The jitter figure-of-merit of the synthesizer is −237.2 dB.

Monolithic 3D Integration With Photosensor and CMOS Circuits Using Ion-Cut Layer Transfer

A thin Si layer transfer process for monolithic 3D (M3D) integration is proposed using hydrogen ion (H <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> ) implantation. The upper Si layer was transferred to CMOS circuits fabricated on the lower substrate by H <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> implantation, oxide-to-oxide bonding, and a cleavage process at low temperature (< 500 °C). The M3D system comprising the photosensor connected to the CMOS device was demonstrated, where the thickness and roughness of the transferred Si layer were determined by H <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> implantation and subsequent processes. The hetero-junctional photosensor was fabricated on the transferred Si layer, which generated the photocurrent ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{\text {ph}}$ </tex-math></inline-formula> ) by light exposure. The photosensor and ring oscillator circuits of the vertical structure implemented by the M3D process generated the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{\text {ph}}$ </tex-math></inline-formula> according to the light exposure intensity and showed different frequency behaviors accordingly. Compared with the continuous device scaling approach, M3D may be an alternative scheme for low-power, high-performance, and multi-functional devices.

A 1.05-to-3.2 GHz All-Digital PLL for DDR5 Registering Clock Driver With a Self-Biased Supply-Noise-Compensating Ring DCO

This brief presents an all-digital PLL (AD-PLL) for a DDR5 registering clock driver (RCD) with a self-biased supply-noise-compensation (SNC) technique. By combining two Nagata current sources that have opposite dependency on supply variations, it offers a constant current to a ring oscillator over a wide range of supply voltage. Thereby, the dynamic voltage droop due to variations in workload is compensated while a voltage margin for mass production is improved. Since the SNC technique operates independently of the PLL loop bandwidth without using feedback, the proposed AD-PLL is free from the stability problem associated with bandwidth overlapping. Quantitative analyses on static and dynamic characteristics of the proposed SNC technique and relevant design considerations are addressed. Fabricated in the 28-nm CMOS technology, the AD-PLL occupies an active area of 0.06 mm2 and consumes 12.1 mW at 3.0 GHz with a 1.1 V supply voltage. The power-supply-noise-attenuation (PSNA) is measured as 40 dB and the integrated rms jitter of 271 fs is observed.

A Variation Aware Jitter Estimation Methodology in ROs Considering Over/Undershoots in NTV Regime

A time-domain jitter estimation methodology considering process-voltage-temperature (PVT) variations of the single-ended ring oscillator (SERO) at an early stage of design is presented for near-threshold voltage (NTV) regime where nonlinearities dominates. For the first time, the model accounts for the jitter due to the over/undershoot region which is critical in the NTV regime. Further, the model uses effective drive current, Ieff model. The Ieff is obtained considering the regions of device operation, instead of using only saturation current for jitter calculation. A time-domain jitter model is developed by considering the change in transition threshold points (TTPs) whose relative values are supply independent and Ieff of each region with the PVT variation, design parameters, and with the introduction of noise in the circuit. The model analyzes the effects of random (white noise) and deterministic (supply, substrate) noise in the NTV regime. This approach is physics/topologybased and is valid for different technologies. Post-layout simulations have been performed on parasitic extracted netlist using CADENCE and HSPICE in STM 65nm CMOS Process Design Kit (PDK) to validate the jitter model in the NTV regime.

Analysis of Self-Heating Effects in Multi-Nanosheet FET Considering Bottom Isolation and Package Options

Self-heating effects (SHEs) of multi-nanosheet FET (mNS-FET) at the 3-nm technology node were analyzed at the device and circuit level considering the introduction of punchthrough-stopper (PTS) doping and bottom oxide (BO), which are substrate processes to reduce leakage current. Changes in the heat path according to the back-end-of-line (BEOL) configuration and package type were also considered. After optimizing the PTS doping and BO process through six case analyses using three-dimensional (3-D) TCAD simulations, SHE characteristics were investigated. As a result, the channel temperature risen due to SHE was larger when BO was applied than when BO was not applied, and that the face-down package was more effective in heat dissipation than the face-up package. Next, the SHE behavior during dynamic operation of logic and analog circuits was analyzed through SPICE modeling, and the effect of this on circuit performance and reliability was analyzed. As a result, in the logic ring oscillator circuit, the SHE shows a slight AC performance degradation of ~1.3%, but in terms of reliability, it causes a decrease in the lifetime of 15.1%–22.1%. In the two types of analog circuits, the possibility of circuit malfunction can be confirmed by SHE, and in terms of reliability, it causes a reduction in lifetime of 53.5%–89.9%. Therefore, it is expected that device and circuit design that can reduce SHE are required in consideration of the various processes analyzed in this work.