Abstract
A ring-oscillator (RO)-based low-jitter digital fractional-N frequency synthesizer is presented. It employs a frequency doubler (FD) that doubles the reference clock frequency, a 2-bit time-to-digital converter (TDC) with optimized thresholds to minimize the quantization error, and a high-resolution digital-to-time converter (DTC) to cancel the quantization error of the delta-sigma fractional divider (FDIV). DTC’s linearity is improved using a piecewise linear (PWL) function-based correction scheme. On-chip digital calibration is extensively used to correct imperfections of the FD, TDC, and DTC. A prototype synthesizer incorporating the proposed techniques and implemented in a 65-nm CMOS produces a 3.2-GHz output clock from a 96-MHz input clock. The worst-case integrated jitter is 306 and 405 fs in integer and fractional-N modes, respectively. The synthesizer consumes 11.7 mW from a 1-V supply of which 7.84 mW is consumed by the oscillator. The jitter figure-of-merit of the synthesizer is −237.2 dB.
Highlights
L OW-jitter fractional-N frequency synthesizers play a crucial role in wireline transceivers
Because the to-digital converter (TDC) quantization error is low-pass filtered by the phase-locked loops (PLLs), a narrow bandwidth may be needed to reduce output jitter degradation
It is composed of a frequency doubler (FD), a PFD, a TDC, a proportional-integral (PI) loop filter, a digitally-controlled RO (DCRO), a sigma-delta () fractional divider (FDIV), and a digitalto-time converter (DTC)
Summary
L OW-jitter fractional-N frequency synthesizers play a crucial role in wireline transceivers. They provide a great deal of flexibility in a multi-lane serializer–deserializer (SerDes) for setting the data rates in a fine-grained manner. Low-jitter fractional-N frequency synthesizers are traditionally implemented using LC-oscillator-based analog phase-locked loops (PLLs) [3]. While they are shown to achieve excellent jitter and spurious performance, they suffer from several drawbacks.
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