A High-Throughput Vernier Time-to-Digital Converter on FPGAs with Improved Resolution Using a Bi-Time Interpolation Scheme

Abstract

A novel ring oscillator-based Vernier-type time interpolation method, known as the fine-timestamp maker, is proposed for field programmable gate array (FPGA)-based time-to-digital converters (TDCs). This method determines lower measurement dead time and improves resolution by using a bi-time interpolation scheme, first presented in this paper. Additionally, a group of cascaded delay units are packaged as an intellectual property core (DU-IP) to form a ring delay line and to adjust its length via the engineering change order (ECO) tool, which makes the adjustment of the ring oscillator’s frequency more linear and less position dependent. A prototype TDC was implemented on a Kintex-7 FPGA. The experimental results demonstrate that a single TDC channel only consumes 35 DFFs, 31 LUTs, and 16 CARRY4 logics after specific adjustment. The results, with a time resolution of 20 ps, dead time of 58 ns, and a root-mean-square error of 15–20 ps, show a significant performance improvement compared to traditional Vernier-type TDCs.