FPGA-based high-performance time-to-digital converters by utilizing multi-channels looped carry chains

Abstract

Time-to-digital converters (TDCs) are core components in many applications and numerous works on this theme have been conducted in recent years. For field programmable gate array (FPGA) based TDCs, their overall performance are still not satisfying when compared with application specific integrated circuit (ASIC) based TDCs. We propose multi-channels looped carry chain TDC architecture in this paper in order to narrow down the performance gap between FPGAs and ASICs. An example TDC prototype implemented on a Stratix III FPGA chip by using the proposed method achieves the resolution below 20 ps, the precision root mean square (RMS) below 15 ps, and the differential non-linearity (DNL) and integral non-linearity (INL) within the range of 2 least significant bit (LSB) peak-to-peak value. This performance is very competitive among all existing FPGA-based designs and close to some ASIC-based TDCs.