RF Figures Of Merit Research Articles

A First Insight to the Thermal Dependence of the DC, Analog and RF Performance of an S/D Spacer Engineered DG-Ambipolar FET

This paper investigates for the first time the temperature dependence of the digital/analog parameters and RF figure of merits (FOMs) of a spacer based reconfigurable field-effect transistor (RFET) and compares the same with the existing RFET topology and other devices which depend on band-to-band tunneling (BTBT) for their on-current generation. It is observed that the output characteristics of the device are less sensitive to the temperature in the BTBT dominated on-state region as compared to the subthreshold one which is thermionic emission dependent. Having a better thermal stability over tunnel field effect transistor (TFET) and significantly lesser Vth roll-off, the proposed device portrays orders of magnitude reduction in parasitic gate capacitances and intrinsic delay as compared to gate-all-around (GAA) and hetero gate dielectric GAA TFET devices over the considered range of temperature, thus assuring higher switching speed for digital applications. Moreover, superior analog/RF performance is also exhibited by the device under consideration for all temperatures in contrast to SiGe, full silicon TFETs, and conventional RFET topology owing to higher BTBT dominance and better gate controllability. Apart from all of these performance gains, the device FOMs are found to be less sensitive to temperature variations making it more suitable for applications where temperature fluctuation is a major concern.

Controlling ambipolarity with improved RF performance by drain/gate work function engineering and using high $$\kappa $$ κ dielectric material in electrically doped TFET: proposal and optimization

This article proposes a novel device structure of electrically doped tunnel FET with drain/gate work function engineering by using hetero-dielectric material for the suppression of ambipolar behavior with improved DC and RF characteristics. For this, a P–I–N type structure was formed over an intrinsic silicon wafer by applying negative and positive voltages to create source and drain regions, respectively. Formation of source and drain regions by the concept of electrical doping is useful for reduction of random doping fluctuations and fabrication complexity. For suppression of ambipolar behaviour, the drain electrode is split into two different metal work functions ( $$\phi _\mathrm{DE1}$$ < $$\phi _\mathrm{DE2}$$ ), which alters the carrier concentration and increases the tunneling barrier at the drain/channel interface. Consequently, the proposed modification in terms of dual work functionality at the drain terminal offers better performance in terms of suppression of negative conductance (ambipolar current) and parasitic capacitances. However, the presence of dual work functionality at the drain electrode causes degradation in ON-state current and RF figures of merit. To resolve these problems, the control gate electrode is further split into two different work functions and uses hetero gate dielectric material, where the gate work function near the source/channel interface is greater than the gate work function near the drain/channel interface. It assists tunneling of carriers at the source/channel junction and improves ON-state current with RF performance. Apart from this, the use of hetero gate dielectric material provides further enhancement in DC and high frequency behaviour of the device.

Performance Evaluation of Bilayer Graphene Nanoribbon Tunnel FETs for Digital and Analog Applications

The recent advancement in the fabrication of narrow graphene nanoribbon with smooth edges has catalyzed the growth of nanoribbon based transistors. Motivated by these advances, we suggest bilayer graphene nanoribbon tunnel field-effect transistors (BLGNR-TFETs) for low voltage digital and analog applications. The device performance is analyzed by quantum transport simulation, based on self-consistent solutions of two-dimensional Poisson's equation and nonequilibrium Green's function formalism. The results indicate that the use of BLGNR-TFET instead of monolayer graphene nanoribbon TFET with very narrow width, increases the ON current and reduces the intrinsic device delay without lowering the ON/OFF current ratio. The BLGNR-TFET for analog/RF applications has provided higher intrinsic gain at very narrow ribbon width; however, very narrow width reduces the cutoff frequency. Furthermore, RF figure of merits are investigated in the presence of external parasitics.

Effect of FIBL in-conjunction with channel parameters on analog and RF FOM of FinFET

In this paper, the effect of fringe induced barrier lowering (FIBL) in-conjunction with channel parameters that includes channel thickness (TSi), channel length (Lg) and lateral straggle (σL) on analog and RF performance of FinFET, have been studied using TCAD mixed-mode Sentaurus device simulator. We focused on the variation in analog (intrinsic dc gain) and RF (cut-off frequency) figure of merit (FOM) of high-K gate dielectric based FinFET with respect to channel parameters. It is observed that the variation in intrinsic dc gain (ΔAV) aggravates with TSi scaling. We also observe a mixed response to the ΔAV with respect to variation in Lg and σL, where ΔAV follows an inverse parabolic behavior peaking at an intermediate value of Lg and σL. Variation in cut-off frequency (ΔfT) on the other hand, is negligible (slightly increases with TSi and decreases with Lg and σL). These properties of channel parameters can be handy in designing of high-K gate dielectric based FinFET for analog circuits.

Influence of Germanium source on dopingless tunnel-FET for improved analog/RF performance

Dopingless (DL) and junctionless devices have attracted attention due to their simplified fabrication process and low thermal budget requirements. Therefore, in this work, we investigated the influence of low band gap Germanium (Ge) instead of Silicon (Si) as a “Source region” material in dopingless (DL) tunnel field-effect transistor (DLTFET). We observed that the Ge source DLTFET delivers much better performance in comparison to Si DLTFET under various analog/RF figure of merits (FOMs), such as transconductance (gm), transconductance generation factor (TGF) (gm/Id), output conductance (gd), output resistance (RO), intrinsic gain (gmRO), intrinsic gate delay (τ) and RF FOMs, like unity gain frequency (fT), gain bandwidth product (GBW) along with various gate capacitances. These parameters were extracted using 2D TCAD device simulations through small signal ac analysis. Higher ION/IOFF ratio (1014) of Ge source DLTFET can reduce the dynamic as well as static power in digital circuits, while higher transconductance generation factor (gm/Id) ∼ 2287 V−1 can lower the bias power of an amplifier. Similarly, enhanced RF FOMs i.e unity gain frequency (fT) and gain bandwidth product (GBW) in Gigahertz range projects the proposed device preference for RF circuits.

RF Performance of Trigate GaN HEMTs

The impact of the trigate GaN high electron mobility transistor (HEMT) body geometry on the device RF performance is investigated by 3-D numerical simulations. The trigate concept is a viable approach to achieve normally off operation and to suppress short-channel effects. The effect of gate length scaling on the RF behavior is studied and guidelines for design improvements are provided. Furthermore, it is shown that trigate HEMTs with improved body design and/or InAlN barriers causing a higher polarization charge than AlGaN can exhibit better RF figures of merit than planar GaN HEMTs.

Performance investigation of heterogeneous gate dielectric-gate metal engineered–gate all around-tunnel FET for RF applications

In this work, the effect of gate metal work function engineering (GME), gate bias and drain bias on the bias dependent parasitic capacitances has been studied. Further, RF Figure of merits (FOMs) such as power gains, cut-off frequency (fT), maximum oscillation frequency (fMax) and intrinsic delay of hetero-dielectric gate-metal-engineered gate-all-around tunnel FET (HD-GME-GAA-TFET) are studied and compared with HD-GAA-TFET. Simulation results show an appreciable improvement in RF FOMs with the application of GME architecture on GAA TFET. Further, it has been observed that GME exhibits 3.76 times enhancement and 0.017 times reduction in cut-off frequency and intrinsic delay respectively as we increase the work function difference, which makes it a promising candidate for low power switching applications. Moreover, the small signal Y-parameters have also been studied which indicates that HD-GME-GAA-TFET is a promising candidate for RF/microwave applications. All the simulations have been done using ATLAS device simulator.

A two-dimensional (2D) analytical subthreshold swing and transconductance model of underlap dual-material double-gate (DMDG) MOSFET for analog/RF applications

The double-gate (DG) metal-oxide-semiconductor field effect transistors (MOSFETs) are the choice of technology in sub -100 nm regime of leading microelectronics industry. To enhance the analog and RF performance of DG MOSFET, an underlap dual-material (DM) DG MOSFET device structure has been considered because, it has the advantages of both underlap as well as that of dual-material gate (DMG). A 2D analytical surface potential, subthreshold current, subthreshold swing as well as transconductance modelling of underlap DMDG MOSFET has been done by solving the Poisson's equation. It has also been found that, numerically simulated data approves the analytically modelled data with commendable accuracy. As underlap length (Lun) increases, a substantial reduction of subthreshold current due to enhanced gate control over channel regime is observed. DMG structure facilitates to improve the average velocity of carriers which leads to superior drive current of the device. The underlap DMDG MOSFET device structure demonstrates an ameliorated subthreshold characteristic. The analog figure of merits (FOMs) such as transconductance (gm), transconductance generation factor (TGF), output conductance (gd), early voltage (VEA), intrinsic gain (AV) and RF FOMs namely cut-off frequency (fT), gain frequency product (GFP), transconductance frequency product (TFP) and gain transconductance frequency product (GTFP) have been evaluated. The aforesaid analysis revels that, the device is best suited for communication related Analog/RF applications.

Part I: High-Voltage MOS Device Design for Improved Static and RF Performance

In this paper, for the first time, the key design parameters of a shallow trench isolation-based drain-extended MOS transistor are discussed for RF power applications in advanced CMOS technologies. The tradeoff between various dc and RF figures of merit (FoMs) is carefully studied using well-calibrated TCAD simulations. This detailed physical insight is used to optimize the dc and RF behavior, and our work also provides a design window for the improvement of dc as well as RF FoMs, without affecting the breakdown voltage. An improvement of 50% in $R_{\mathrm{{\scriptscriptstyle ON}}}$ and 45% in RF gain is achieved at 1 GHz. Large-signal time-domain analysis is done to explore the output power capability of the device.

Analytical surface potential modeling and simulation of junction-less double gate (JLDG) MOSFET for ultra low-power analog/RF circuits

In this paper, a simple structure for short channel junction-less double gate (JLDG) MOSFET is proposed. Further expression for surface potential of JLDG has been derived using 2D Poisson׳s equation. Based on the proposed analytical model for surface potential distribution along channel thickness and channel length is derived. The proposed junction-less MOSFET has no p-n junction as the doping of channel is same to that of Source/Drain region. The analytical model is compared with numerical solution using ATLAS device simulator. The result shows the variation of channel potential with channel length, channel thickness, doping concentration and applied gate bias. Further, in this paper the analog performance and RF figure of merits (FOMs) have been investigated. The purpose of this research is to provide a physical explanation for improved analog and RF performance exhibited by the device. In this paper major FOMs such as trans-conductance (gm), output conductance (gd), early voltage (VEA), intrinsic gain (AV), trans-conductance generation factor (TGF), cut-off frequency (fT), trans-conductance frequency product (TFP), gain frequency product (GFP), gain trans-conductance frequency product (GTFP) are analyzed. The simulation result shows that the JLDG exhibit a higher trans-conductance, higher cut-off frequency and lower drain conductance.

Estimation of analog/RF figures-of-merit using device design engineering in gate stack double gate MOSFET

In this paper, the analog performance as well as some new RF figures of merit (FOMs) are reported for the first time of a gate stack double gate (GS-DG) metal oxide semiconductor field effect transistor (MOSFET) with various gates and channel engineering. The comparison is made through various performance metrics between single material (SM) GS-DG, dual material (DM) GS-DG, and dual material single halo (DM-SH) GS-DG MOSFETs. The key idea behind this investigation is to provide a physical explanation for the improved analog and RF performances exhibited by the device. The major figures of merit (FOMs) such as transconductance (gm), output conductance (gd), transconductance generation factor (TGF), early voltage (VEA), intrinsic gain (AV), cut off frequency (fT) are analyzed in this paper. The VEA and TGF for p-MOSFET with above technologies are also systematically investigated with the help of extensive device simulation, i.e. TCAD (Technology Computer Aided Design). The DM-DG devices are known to have significantly better performances as compared to SM counterparts. The analysis shows an opportunity for realizing high performance analog and RF circuits with the device proposed in this paper. The DM-DG configurations can be preferred over SM-DG as they show 48.53% improvement in fT, 25.54% in AV and more than 90% in VEA.

Impact of the lateral straggle on the Analog and RF performance of TFET

In this work, the effect of the variation in lateral straggle on TFETs performance is demonstrated. The ion implantation technique during fabrication process causes the extension of dopants from source/drain region towards the channel. Even though the use of non-zero tilt angle at the time of ion implantation is necessary to avoid the channeling effect, however, series resistance, threshold voltage roll offs, switching speed and effective channel length of the device get affected by the non abrupt doping profile at the source/drain-body junction. It is established earlier that TFET is very convenient for Analog/RF application owing to its below 60mV/decade subthreshold swing and reduced short channel effects. In order to show the effect of lateral straggle on TFET’s performance, various Analog figure of merits (FOMs) such as drain current (Id), transconductance (gm), transconductance generation factor (gm/Id), output resistance (Ro), intrinsic gain (gmRo) and RF figure of merits (FOMs) like unity gain cutoff frequency (fT), transit frequency of maximum available power gain (fMAX) are investigated for the variation in straggle parameter from 0nm to 5nm in order to optimize the device performance. The circuit performance of the device for different lateral straggle is carried out using common source amplifier.

Impact of underlap and mole-fraction on RF performance of strained-Si/Si1−xGex/strained-Si DG MOSFETs

In this paper, a systematic RF performance analysis of double-gate strained silicon (DGSS) nMOSFETs is presented. The analysis is focused upon impact of Germanium mole-fraction variation on RF performance of underlap engineered DGSS nMOSFET. The RF performance of the device is analysed as a function of intrinsic RF figure of merits (FOMs) including non-quasi static effects (NQS). The RF FOMs are represented by the intrinsic gate to source/drain capacitance (Cgs and Cgd) and resistance (Rgs and Rgd), the transport delay (τm), the intrinsic inductance (Lsd), the cut-off frequency (fT), and the maximum oscillation frequency (fMAX). The results of the study suggested a significant improvement in the device performance, up to 40% increase in Germanium mole fraction (χ).

The performance measure of GS-DG MOSFET: an impact of metal gate work function

The quantitative assessment of the nanoscale gate stack double gate (GS-DG) MOSFET performance values are numerically calculated with different gate metal work functions (Φm = 4.52 eV, 4.6 eV, 4.7 eV). The effect of electrostatic control on dc, analog and RF figures of merit (FOMs) which includes subthreshold slope (SS), drain induced barrier lowering (DIBL), transconductance generation factor (TGF), early voltage (VEA), intrinsic gain (AV), cut off frequency (fT) and transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP) have been investigated for the model GS-DG MOSFET. Higher TGF and AV was achieved with Φm = 4.6 eV for the device. For a better comparison among the analog/RF FOMs, the threshold voltage (Vth) is maintained at a constant value for different work function cases. To achieve a constant Vth, the channel doping (NA) and source/drain doping (ND) is tuned accordingly for all device cases. Superior fT which is due to higher transconductance (gm) and lower output conductance (gd), was observed for the device. In addition, better gain performances i.e. GFP and GTFP were achieved resulting from improved gm. Thus, the device structure modelled with Φm of 4.6 eV can be considered as a better candidate for analog and RF circuit applications.

On the Use of Static Temperature Measurements as Process Variation Observable

In this paper we present the use of static temperature measurements as process variation observable. Contrary to previously published thermal testing methods, the proposed methodology does not need an excitation signal, thus reducing test cost and improving built-in capabilities of thermal monitoring. The feasibility of the technique and a complete test methodology is presented using a narrowband LNA as example. Finally, a complete electro-thermal co-simulation test bench between the LNA and a differential temperature sensor embedded in the same silicon die is presented in order to validate the results. Results prove that RF figures of merit can be extracted from DC temperature measurements done without loading or exciting the RF circuit under test.

Key Aspects in Modeling of Thin Epi SOS Technology With Application of BSIMSOI

This work addresses the device modeling challenges of production-quality, state-of-the-art, silicon-on-sapphire (SOS) processes. Differences between SOS, silicon-on-insulator (SOI), and bulk CMOS are highlighted, with emphasis on the key differences in the modeling methodology. For RF and low-power applications, SOS has distinct advantages over SOI, such as reduced parasitics, better linearity, and enhanced electrical isolation. Yet little is reported in the literature about modeling of a commercially viable SOS process. Though originally developed for SOI, it is demonstrated that the BSIMSOI model can adequately represent SOS MOSFETs, including fully and partially depleted devices. For RF switch applications, RON and COFF are captured with reasonable accuracy. An additional RF figure of merit, fT, is also reasonably well modeled, yielding peak values in the 40-50 GHz range.

A 5000 h RF life test on 330 W RF-LDMOS transistors for radars applications

A reliability test bench dedicated to RF power devices is used to improve 330 W LDMOS in a radar conditions. The monitoring of RF power, drain, gate voltages and currents under various pulses and temperatures conditions are investigated. Numerous duty cycles are applied in order to stress LDMOS. It shows with tracking all this parameters that only few hot carrier injection phenomenon appear with no incidence on RF figures of merit ( P out or PAE). Robustness and ruggedness are shown for LDMOS with this bench for radar applications in L-band.

High-temperature DC and RF behaviors of partially-depleted SOI MOSFET transistors

This work presents the high-temperature DC and RF behaviors of partially-depleted SOI MOSFETs. DC and RF figures of merit are deeply investigated, both analytically and experimentally, to provide a complete study of high-temperature performance and a comparison between floating-body and body-tied transistors. A highly stable RF performance is noticed especially for cutoff frequency and intrinsic elements for temperature as high as 250 ° C .

RF Performance of Strained SiGe pMOSFETs: Linearity and Gain

In this work, we investigate RF performance of strained-SiGe pMOSFET because of its easy integration into planar architecture than strained-Si nMOSFET. RF figure of merits considered include linearity, intrinsic gain and g/sub m//I/sub d/. To optimize RF performance, variations of SOI thickness (t/sub si/) and Ge concentration in the channel are investigated. Furthermore, since graded channel (GC) MOSFET has been proposed as a candidate of RF application by B. Cheng et al., 1998, a graded strained-SiGe channel pMOSFET is studied comparatively for RF analysis.