Reference Clock Research Articles

A low-jitter and low-phase noise switched-loop filter PLL using fast phase-error correction and dual-edge phase comparison technique

This paper presents a low-jitter and low-phase noise type-II charge pump and switched-loop filter-based (SLF) phase-locked loop (PLL) with a fast phase error correction technique (FPEC) and a newly proposed dual-edge phase comparator (DEPC). To improve the phase noise, the bandwidth of the proposed PLL is extended to fREF/5 using the proposed DEPC. It consists of four D flip-flops in true single-phase clock (TSPC) logic, four current-mode logic-based inverters, and two logic OR gates. Unlike conventional DEPCs, the proposed DEPC has a small reset pulse width duration and negligible blind zone, and due to this, it can perform at higher frequencies along with an increased phase detection range. The proposed architecture is implemented for a 2.4 GHz output frequency that embodies DEPC and SLF using the FPEC technique in an 180-nm Semi-Conductor Laboratory (SCL) CMOS process. The proposed DEPC can work up to a maximum of 3.45 GHz frequency with 145 ps of reset delay. The proposed PLL accomplishes the 40 MHz bandwidth with a 200 MHz reference clock. The simulated rms jitter integrated from 10 kHz to 100 MHz and the phase noise of the output signal at an offset of 1 MHz are 860 fs and −122 dBc/Hz respectively. The proposed architecture occupies an area of 0.032 mm2 and consumes 8.2 mW from 1.8 V power supply.

An event‐driven model of fractional‐N CPPLL based FMCW synthesizers

AbstractThis paper proposes an improved event‐driven (ED) model to improve the simulation efficiency of a mixed‐signal charge‐pump phase locked loop (CP‐PLL) design for a frequency‐modulated continuous‐wave (FMCW) chirp generation. The improvement mainly comes into three parts. First, we update the data only when it changes during the previous trigger. Second, we save the data at the triggering moment of the reference clock to achieve uniform sampling for better noise characterization. Furthermore, we propose a simplified model that is specifically optimized for the third‐order loop filter (LF). This article presents a detailed design flow of the improved ED model, and we apply it to the simulation of the FMCW chirp generation. Compared to the conventional transistor‐level simulation, our proposed model reduces the simulation time to less than 1 s, which leads to a reduction of the simulation time by five or six orders of magnitude.

Remote Residual Instability Evaluation of Comb-Based Precise Frequency Transmission for Optical Clock

Optical clocks can be used as the absolute frequency reference due to their high accuracy and stability. In a precise optical clock transmission system, the instability loss of the link is usually evaluated by beating the remote optical signal with the reference clock, which is not suitable for real frequency distribution applications. Therefore, it is necessary to assess the performance directly at the remote site for the optical frequency transfer, because the two sites of the link are usually not co-located. In this paper, we proposed a comb-based remote residual instability evaluation scheme. Two coherent optical combs with different wavelengths were extracted from a frequency stable comb and transmitted after multiplexing. The residual instability was evaluated directly at the remote site by measuring the phase fluctuation difference between the two combs. We achieved 8.61 × 10−19 at 40,000 s over a 10 km fiber link, reaching the instability of optical clocks. These results revealed that our scheme can evaluate optical clock frequency transmission directly at the remote site, which made the method truly practical.

A 1-V 9.6-GHz charge-pump PLL with low RMS-integrated jitter

A low-power low-jitter phase-locked loop (PLL) with phase noise improvement for radio frequency transceivers is presented in this paper. The in-band phase noise and out-of-band phase noise are both reduced due to the time-amplifying technique and the class-C voltage-controlled oscillator (VCO), respectively. In addition, a low current mismatch charge pump (CP) is used here to guarantee a low reference spur. The proposed PLL is fabricated in a 65-nm CMOS mixed-signal process with an area of 0.220 mm2, and the reference clock is 150 MHz. The measurement results show that this PLL operates at 1-V supply voltages and achieves 8.5–10.3-GHz tuning range, 407.807-fs integrated jitter at 9.6 GHz, 7.20-mW total power consumption, resulting in a −239.22-dB figure-of-merit (FoM). The measured reference spur is −51.27 dBc at a 150-MHz offset frequency.

Design of charging station and optimization of oscillation circuits for new energy vehicles

In order to ensure good charging performance of new energy vehicles, the charging station was designed and the relevant oscillation circuits were optimized. The function and structure of the charging station was determined, and through a hierarchical framework, not only the success rate factor could be corrected, but also a resonant converter was combined to achieve efficient charging over a wide battery voltage range. The linear charging management chip was adopted, which integrated high-precision constant voltage source, temperature monitoring, charging status display, and battery charging completion termination function. The changes in excitation current and switching frequency during the charging process were studied, and the optimization basis for the relevant circuits was determined. A trigger was added to the input end of the oscillator to filter the input signal, which improved the accuracy of the RC oscillator cycle. The clock reference oscillation circuit and stable voltage power supply circuit were optimized. In order to verify the effectiveness of the proposed electronic control design, a hardware platform for the test of DC output characteristics was built. The results indicate that the output voltage waveform can effectively meet the working requirements.

A Fast-Lock Variable-Gain TDC-Based N/M-Ratio MDLL Clock Multiplier

A variable-gain time-to-digital converter (TDC)-based multiplying delay-locked loop (MDLL) clock multiplier featuring fast-locking and programmable N/M-ratio frequency multiplication capability is presented in this paper. The proposed all-digital programmable N/M-ratio MDLL achieves fast-locking capability by adopting a new variable-gain TDC. In conventional fixed-gain TDC-based MDLLs, the lock time increases as the value of the multiplication factor N decreases. However, the proposed variable-gain TDC can minimize the MDLL lock time by adjusting the TDC gain according to the change in N value. Implemented in a 40 nm 1.1-V CMOS process, the proposed all-digital MDLL clock multiplier generates output clock frequencies ranging from 0.65 to 3.2 GHz, with programmable N/M ratios of N = 5 to 16 and M = 1 to 8. It achieves a fast lock time of only 3 × M (=9) reference clock cycles when N/M = 10/3 at 2.0 GHz and demonstrates a simulated peak-to-peak jitter of 3.16 ps at 3.2 GHz when N/M = 16/3. Additionally, it occupies an active area of only 0.02 mm2 (=200 μm × 100 μm) and consumes a power of 2.3 mW at 1.0 GHz.

Clock noise reduction in geometric time delay interferometry combinations

Time-delay interferometry (TDI) is a critical data post-processing technique in space-borne laser interferometer gravitational wave detection, which is developed to suppress the overwhelming laser phase noise below the instrumental noise floor by time-shifting and synthesizing the interferometric data streams. There are virous kinds of TDI combinations, and geometric TDI, as a special means to search TDI combination, has been widely used because of its clear physical significance, i.e. constructing virtual equal-arm interferometer to realize an excellent differential performance of the laser phase noise. To achieve the desired noise level, it is necessary to further suppress the phase fluctuations of the onboard ultra-stable oscillators (USO) used as reference clocks. In this paper, we analyze the characteristics of geometric TDI clock noise residual, and formulate it into a general expression. We find the intrinsic equal-arm length constraint of geometric TDI is a sufficient condition for clock noise reduction, which makes the clock noise terms only appear in differential form. Based on this, we propose a clock noise reduction scheme. Compared with the existing algorithms, our method benefits from the sufficient condition to avoid the problem that the clock noise terms without any time-shift operators cannot be properly handled.

On the Synchronous Ethernet for a Massive Networking Deployment: Insight Into a Tailored Cosimulated Testbed

Digital communications have a minimum synchronization requirement: the end user of a telecommunication system has to lock into the right bit rhythm sent by the other connection partner. Nevertheless, synchronization in the telecommunication context turns out to be broader than two connection partners locally linked: the suitable feed of a standard time, within many telecommunication domains, has vital importance for many applications to properly handle the demanded network functionalities. The time feed in multidomain scenarios makes a time path, which becomes a nested built-in network. Generally, the data distribution follows the time path in many telecommunication systems. However, the data path may not follow the time path for all scenarios and could partially follow some network branches, usually at the network border. To ensure efficient and controllable synchronization, we focus on the study of time paths. This article provides a first insight into a tailored cosimulated testbed, implemented to determine the time path behavior in terms of jitter and to supervise the drift from the primary reference clock (PRC) with more than 20 cascaded nodes, the maximum achievable cascaded depth within the current G.8262 standard. This cascading must meet the requirements of the International Telecommunication Union (ITU-T) standards G.8262/G.8261 in terms of long-term jitter (wander) and short-term jitter (jitter) to ensure a tolerable drift compared with the central clock. In particular, for Synchronous Ethernet (SyncE), the standard does not provide possible limits for the jitter beyond 20 synchronized nodes. The numerical results, with the extended number of nodes, show that this scenario remains feasible, the parameters being below the masks proposed by the standards.

Design and Verification of Serial Communication Interface for High Speed Data Transfer

Abstract: Inter-Integrated Controller is a crucial interface for device communication. I 2 C is utilized as an interface between EEPROMS since they need an interface for communication. The design's operation has been confirmed, and there has been no data transfer interruption. The proposed verification environment is designed using system Verilog which includes the constrained randomization for the stimulus generation. In the proposed system, a modified FSM is used in the data transfer process between the master and slave EEPROM. I2C typically operates at a 100MHz clock frequency in an FPGA with a reference clock used in the system creates a slower clock which is completely configurable in the TB for the bits to get transferred. The finite state machine also handles the acknowledge response where it stays in the same state until the acknowledge is received unlike going to the starting state. A memory controller was used to control the I2C transactions with the EEPROM slave and the data transfers were executed as expected. System Verilog is the HDL used for the design and creating the verification environment with Xilinx Vivado 2020.02 as the IDE used to run the simulations

Clock synchronization based on pulse with propagation delay eliminated in wireless sensor networks

AbstractClock synchronization is indispensable for numerous applications of wireless sensor networks (WSNs). When no common reference clock is available, the nodes must employ distributed synchronization techniques. This paper proposes, a distributed pulse‐based clock synchronisation approach, wherein the propagation delay is eliminated through signal ping‐pongs between neighbouring nodes. Such an approach can jointly estimate the clock skew and offset without requiring any reference clock. The whole synchronization process is completed at the physical (PHY) layer, effectively avoiding the random delay caused by packet queuing and retransmission. Simulation results show that the proposed approach can achieve higher synchronization accuracy compared with other existing methods.

A 208-MHz, 0.75-mW Self-Calibrated Reference Frequency Quadrupler for a 2-GHz Fractional-N Ring-PLL in 4-nm FinFET CMOS

This paper presents a 208-MHz, 0.75-mW selfcalibrated reference frequency quadrupler (RFQ), which provides a 4x higher reference clock with minimal deterministic frequency error. The digital-assisted calibration technique is exploited to compensate wide range of frequency and duty cycle errors and to reduce the noise degradation of analog calibration loop. Also, instead of utilizing a duty cycle corrector for 2x clock, reusing a delay cell reduces the power consumption by 50%. The fractional-N ring-PLL with the proposed RFQ was implemented in a 4nm FinFET CMOS process. The active area of the RFQ is 0.0175mm2 while the whole PLL occupies the area of 0.109mm2. By using the RFQ, the measured RMS-jitter of the PLL is definitely improved from 6.6ps to 3.35ps at 1.92GHz output frequency.

Analysis and design approach of wideband digital‐based feedforward ring oscillators

AbstractMulti‐protocol applications and complex systems‐on‐chip demand several clock sources to fulfill all data‐rate requirements. Among the different types of clock sources, LC oscillators dominate the high data‐rate communication standards where frequency stability is a major constraint. In contrast, ring oscillators are preferred for legacy support applications due to their wider tuning range and where stability is not a constraint. Since stability enhancement techniques have been already implemented to ring oscillators, increasing the tuning range of a single ring clock reference might fulfill a broad margin of data rates. This paper presents an analysis and a design approach of wideband digital‐based oscillators based on secondary feedforward paths to support most of the data‐rate requirements inside systems‐on‐chips. Here, we present the inclusion of these auxiliary loops as a tuning range enhancement technique to reduce the total number of required clock references. The presented analysis comprises piece‐wise functions able to accurately predict an FDRO oscillation frequency. Using the piece‐wise model, we present a 15,000 12‐track standard‐cell scalable feedforward oscillator. Auxiliary feedforward inverters allow a maximum 1.5 GHz frequency and a 3 tuning range enhancement while enabling a 100 kHz minimum oscillation frequency. The proposed oscillator occupies an area of 0.05 mm2 in a 180 nm CMOS pure digital node and achieves a 41 ps@1.25 GHz RMS jitter of and a −121 dB FOM.

Design of a Clock Doubler Based on Delay-Locked Loop in a 55 nm RF CMOS Process

In this paper, for the wireless network, wearable device, and Internet of Things (IoT) markets, a delay-locked loop (DLL) is used to implement accurate multiplication for a reference clock and the frequency of various applications through an edge combiner (EC). A simpler structure is more sensitive to process, voltage, and temperature (PVT), so DLL complements itself quickly in the feedback system and improves the stability of the final output. The proposed DLL-based multiplier can prevent harmonic lock generation using a first phase canceller (FPC), thus compensating for faster lock time. The circuit is built with a 55 nm CMOS process and has a chip area of 0.0225 mm2. The proposed design achieves a total power consumption of 0.48 mW at the 30.72 MHz operating clock frequency, and the clock duty can also operate stably from 15 to 75%.

Clock Synchronization and Timestamping of Data on Acquisition at the Wellsite: Guidelines and Recommendations

Summary Due to the nature of drilling operations, there are several companies collecting data at the rig. The data acquisition system of each company applies its own timestamp to the data. Subsequent aggregation of data (for example, in a data repository) relies on synchronized timestamps applied to the different data sources to correctly collate the data. Unfortunately, synchronized timestamping is rarely achieved. In this paper, we document the different sources of errors in timestamping of data and provide guidelines to help mitigate some of these causes. There are many reasons for the unsynchronized timestamping of data from different sources. It can be as simple as clock synchronization at the rig; each data-providing or -producing company has an independent clock. It can also be due to where the timestamp is applied, for example, at the data source or on data reception. Additionally, it can be due to how the timestamp is applied—at the start of the sampling interval, the midpoint, or the end. Some of the communication methods used at the wellsite, such as mud pulse telemetry that is used to transmit downhole measurements to the surface, have a high, nonstationary latency and the actual acquisition time may vary significantly from the received time. Not correcting the reception time for the transmission delay can result in erroneous timestamping of downhole-acquired data. Timestamping of derived data (data computed from two or more sources) is problematic if the data sources are unsynchronized. Synchronization of clocks within the data acquisition network is therefore extremely important. The resolution of time synchronization depends on purpose; motion control of the rig equipment (for example, the hoist) demands high-resolution timekeeping. However, for the purposes of timestamping acquired data, synchronization to a network time server (a computer with access to a reference clock that distributes the time of day to its client computers over a network) with a resolution of 1 millisecond is sufficient. The issue is agreeing on the common source of time (the reference clock) and agreeing on the passage of time signals through network firewalls. Timestamping is a more involved matter, calling for agreement on standards and, if possible, a computer-interpretable description of the time-related information associated with real-time data. In this paper, we describe in some detail sender vs. receiver timestamping, the downhole to surface timestamp chain, and timestamping of derived data. Systems automation and interoperability at the rigsite—allowing plug-and-play access to equipment and applications—rely on an agreed-upon network synchronization scheme and timestamping methods and standards. Indeed, designing applications that must handle uncertain time adds considerable complexity and cost, not to mention the impact on accuracy and reliability. We present an ordered approach (or guidelines) to a quite resolvable problem. In the last section of the paper, we use a semantic network approach (a semantic graph) to describe relationships for clock synchronization and timestamping (the guidelines and recommendations developed in this paper). A complete description of the semantic vocabulary is provided in an appendix. This makes these guidelines and recommendations digital—able to be interpreted by digital devices—and therefore implementable and auditable.

Trigger Timing Interface for the Read-Out Upgrade of the Belle II DAQ

To improve data throughput of the Belle II data acquisition we are upgrading the CPU-based COPPER system with a PCIe40 board carrying Arria 10 FPGA. Since one of the main functionalities of the new system is event building in FPGA, the read-out system must be synchronized with the front-end electronics. This task is performed by the bidirectional trigger timing distribution system. During system commissioning, we prepared several versions of the interface to this system. In the initial version of the interface, we ported the code from Xilinx FPGAs to Arria 10. This revision also introduces monitoring of the status for multiple channels and a ring buffer to distribute trigger information to all channels in parallel. To improve stability under external noise, we implemented a clock-data recovery using an independent on-board oscillator as a reference clock in the next revision of the interface. We are also developing a version utilizing a high-speed serial transceiver to replace CAT-7 RJ45 cables with optical fibers. The system commissioning started in 2021 with a few detectors and will be completed after the long shutdown 1 of SuperKEKB in 2023. In this paper, we present the architectures of the interface to the trigger timing system implemented in the PCIe40 board and the system performance in the experiment.

Design of Clock Synchronization of Base Station by Using 8A34002

The stability of the entire base station depends on the synchronization of the base station’s clock. The clock synchronization management chip 8A34002 supports SyncE Ethernet and IEEE 1588. In this architecture, the GPS receiver, SSI, and master/slave switching device all emit PPS/TOD signals. PPS/TOD signals are input into the FPGA, which outputs one PPS/TOD signal. The PPS/TOD signal enters 8A34002 in this design scheme, and the DPLL of 8A34002 provides filtering and clock-following output. The 8A34002‘s signal output is used as the system’s clock after processing. The switching chip, X86 main control chip, and BBU base station board are all driven by the system clock, which serves as a reference clock. The 8A34002 uses four DPLLs, one each for the SyncE, PTP, GNSS, and test functions.

New Clock Distribution System Based on Clock-Duty-Cycle-Modulation for Distributed Data-Aquisition System

This paper presents a clock distribution system based on a clock-centric modulation technique called clock-duty-cycle-modulation (CDCM) using the IOSERDESE2 primitives of Xilinx field programmable gate array (FPGA). The implemented CDCM techniques, CDCM-10-1.5 and CDCM-10-2.5, transfer 1-bit and 2-bit data per clock cycle by changing the trailing edge positions, respectively. This is the first work to succeed transmitting multi-bits per clock cycle by the CDCM. The developed system consists of the CDCM-based transceiver and the link layer protocol. All the components are implemented using the regular bunk functions in FPGA. The system is independent from a FPGA high-speed serial transceiver and does not require a clock data recovery circuit. In this work, two clock generators were utilized for clock recovery; one is a jitter cleaner IC, CDCE62002 from Texas Instruments, and the other is mixed-mode clock manager (MMCM) in FPGA. The 8-bit incremental data was transmitted by the CDCM modulated clock signal through an optical fiber. The jitters of the clock signals recovered by CDCE62002 were 5.8 and 6.8 ps in standard deviation for CDCM-10-1.5 and CDCM-10-2.5, respectively, when the reference clock frequency was 125 MHz. The averaged phase change of the recovered clock signal during the data transmission was smaller than 10 ps with respect to the clock phase recovered from the signal with the duty cycle of 50%. The obtained bit-error-rate (BER) was smaller than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-13</sup> .

An Implantable Bio-Signal Sensor SoC with Low-Standby-Power 8K-Bit SRAM for Continuous Long-Term Monitoring

Individualized treatment of chronic diseases opens up great opportunities for implantable biosensor systems capable of tracking vital signals over long periods of time. To this end, low-power techniques in standby mode and the efficient utilization of storage space will be important issues for the implementation of such rechargeable implants with a built-in memory. This paper presents key circuit techniques, including a leakage-current-based clock generator that eliminates the need for an internal reference clock source, a low-standby-power 8Kbit SRAM with negative wordline and dynamic supply voltage scaling, and an adaptive sensing scheme to improve storage space utilization. When implemented with commercial 180 nm CMOS technology for the circuit simulation, approximately 70% (100 nW) of power dissipation was reduced from internal clock source, about 70% of power consumed by 8Kbit SRAM was saved, and the storage space utilization was improved by about 42.8%. In the end, the proposed implantable biosensor SoC consumes about 82.5 nW of standby power, saving about 42% from the previous approach and can last for 2.5 days using a 5 uAh thin-film battery (CYMBET® 1.7 × 2.2 mm2).

Reference clock impact on GNSS clock outliers

Abstract With the advent of the Global Navigation Satellite System (GNSS), the need for precise and highly accurate orbit and clock products becomes crucial in processing GNSS data. Clocks in GNSS observations form the basis of positioning. Their high quality and stability enable high accuracy and the reliability of the obtained results. The clock modelling algorithms are continuously improved; thus, the accuracy of the clock products is evolving. At present, 8 Analysis Centers (ACs) contribute to the International GNSS Service final clock products. These products are based on GNSS observations on a network of reference stations, where for a given day one of the reference station clocks is the reference clock. In this paper, the authors determined the impact of the reference clock on the quality of clock product, especially outliers, for the first time. For this purpose, the multi-GNSS final clock products provided by the Center for Orbit Determination in Europe (CODE) for the period 2014–2021 (1773–2190 GPS week, 2921 days) were analysed. Analysis shows that by applying the Median Absolute Deviation (MAD) algorithm for outlier detection, the Passive Hydrogen Maser (PHM) clock installed on board the GALILEO satellites have the lowest level of noise, whereas the Block IIR GPS satellite launched in 1999 appears to have the highest levels of noise. Furthermore, the GNSS station OHIE3, when used as a reference clock, generates an increase in the level of noise, especially noticeable on the G09 and E03 satellites.

A low jitter fractional PLL with offset current charge pump

A low jitter fractional phase-locked loop (PLL) with high quality local oscillator signal for RF transceiver is presented in this paper. Compared with the traditional structure, not only the gated-offset linearization technique is adopted to improve the linearity of the charge pump (CP), but also the sampling filter is used to further reduce the output ripple of the charge pump. The voltage-controlled oscillator (VCO) adopts the tail resistor and second harmonic filter structure to reduce its noise level. The circuit is implemented in a standard 28 nm CMOS process, and the reference clock frequency is 95.76 MHz, which is provided by an integrated crystal oscillator. The chip test results show that the locking frequency range of the PLL is located between 2.42GHz and 3.27 GHz. The phase noise measured at the center frequency of 3.27 GHz at 1 MHz frequency offset is −122 dBc/Hz, RMS jitter is 286 fs, the chip area is 0.78 mm2, and the core current consumption of the PLL is 67.2 mA.