Analysis and design approach of wideband digital‐based feedforward ring oscillators

Abstract

AbstractMulti‐protocol applications and complex systems‐on‐chip demand several clock sources to fulfill all data‐rate requirements. Among the different types of clock sources, LC oscillators dominate the high data‐rate communication standards where frequency stability is a major constraint. In contrast, ring oscillators are preferred for legacy support applications due to their wider tuning range and where stability is not a constraint. Since stability enhancement techniques have been already implemented to ring oscillators, increasing the tuning range of a single ring clock reference might fulfill a broad margin of data rates. This paper presents an analysis and a design approach of wideband digital‐based oscillators based on secondary feedforward paths to support most of the data‐rate requirements inside systems‐on‐chips. Here, we present the inclusion of these auxiliary loops as a tuning range enhancement technique to reduce the total number of required clock references. The presented analysis comprises piece‐wise functions able to accurately predict an FDRO oscillation frequency. Using the piece‐wise model, we present a 15,000 12‐track standard‐cell scalable feedforward oscillator. Auxiliary feedforward inverters allow a maximum 1.5 GHz frequency and a 3 tuning range enhancement while enabling a 100 kHz minimum oscillation frequency. The proposed oscillator occupies an area of 0.05 mm2 in a 180 nm CMOS pure digital node and achieves a 41 ps@1.25 GHz RMS jitter of and a −121 dB FOM.