Design of Clock Synchronization of Base Station by Using 8A34002

Abstract

The stability of the entire base station depends on the synchronization of the base station’s clock. The clock synchronization management chip 8A34002 supports SyncE Ethernet and IEEE 1588. In this architecture, the GPS receiver, SSI, and master/slave switching device all emit PPS/TOD signals. PPS/TOD signals are input into the FPGA, which outputs one PPS/TOD signal. The PPS/TOD signal enters 8A34002 in this design scheme, and the DPLL of 8A34002 provides filtering and clock-following output. The 8A34002‘s signal output is used as the system’s clock after processing. The switching chip, X86 main control chip, and BBU base station board are all driven by the system clock, which serves as a reference clock. The 8A34002 uses four DPLLs, one each for the SyncE, PTP, GNSS, and test functions.