A low jitter fractional PLL with offset current charge pump

Abstract

A low jitter fractional phase-locked loop (PLL) with high quality local oscillator signal for RF transceiver is presented in this paper. Compared with the traditional structure, not only the gated-offset linearization technique is adopted to improve the linearity of the charge pump (CP), but also the sampling filter is used to further reduce the output ripple of the charge pump. The voltage-controlled oscillator (VCO) adopts the tail resistor and second harmonic filter structure to reduce its noise level. The circuit is implemented in a standard 28 nm CMOS process, and the reference clock frequency is 95.76 MHz, which is provided by an integrated crystal oscillator. The chip test results show that the locking frequency range of the PLL is located between 2.42GHz and 3.27 GHz. The phase noise measured at the center frequency of 3.27 GHz at 1 MHz frequency offset is −122 dBc/Hz, RMS jitter is 286 fs, the chip area is 0.78 mm2, and the core current consumption of the PLL is 67.2 mA.