A 1-V 9.6-GHz charge-pump PLL with low RMS-integrated jitter

Abstract

A low-power low-jitter phase-locked loop (PLL) with phase noise improvement for radio frequency transceivers is presented in this paper. The in-band phase noise and out-of-band phase noise are both reduced due to the time-amplifying technique and the class-C voltage-controlled oscillator (VCO), respectively. In addition, a low current mismatch charge pump (CP) is used here to guarantee a low reference spur. The proposed PLL is fabricated in a 65-nm CMOS mixed-signal process with an area of 0.220 mm2, and the reference clock is 150 MHz. The measurement results show that this PLL operates at 1-V supply voltages and achieves 8.5–10.3-GHz tuning range, 407.807-fs integrated jitter at 9.6 GHz, 7.20-mW total power consumption, resulting in a −239.22-dB figure-of-merit (FoM). The measured reference spur is −51.27 dBc at a 150-MHz offset frequency.