Proposed Logic Circuits Research Articles

High Performance Energy-Efficient Leakage-Tolerant Dual Keeper Pseudo Domino Logic

In this paper, an improved high performance energy-efficient leakage-tolerant dual keeper pseudo domino logic circuit is proposed. Circuit design methodologies such as pseudo domino, stacking effect and inverted clock-controlled dual keeper are used in the proposed work for significant reduction of the circuit’s propagation delay and leakage current. Using pseudo-domino logic voltage swing at the output is reduced, stacking effect reduces the leakage current and charge sharing issues in the circuit are reduced by an inverted clock-controlled dual keeper circuit. Leakage current in the proposed circuit is decreased by 21.9%, 20.8%, 71.6%, 52.4% and 57.5% to the conventional logic, DOIND logic, DVT DOIND logic, DFD logic and C3D domino logic, respectively at a 27°C temperature and 1GHz clock frequency. Similarly, delay in the proposed circuit is reduced by 83.3%, 80.1%, 89.8%, 81.3% and 81.5% in comparison to conventional logic, DOIND logic, DVT DOIND logic, DFD logic and C3D domino logic circuit, respectively. Performance metrics like power dissipation, delay, PDP, leakage current, static power, and EDP of the proposed circuit are analysed and compared with the existing domino logics. Monte-Carlo simulation is performed using 1000 samples to analyse the performance of the proposed circuit. The proposed logic circuit is also tested against temperature and process variations. The median values of the proposed buffer circuit’s power and delay are 5.6µW and 1.28ps, respectively and the standard deviation of average power and propagation delay are 633.62nW and 84.37fs, respectively at 27°C and 1GHz clock frequency.

Active loaded source-coupled logic: Applications and performance comparison

In this paper, we provide an extensive analysis of the newly introduced Active Loaded Source-Coupled Logic (ALSCL) family, which is a single-ended type of logic gate family with source-coupled circuit working principles. The proposed source-coupled logic family has analog-friendly behavior similar to previous source-coupled logic circuits, however, the proposed circuit structure has a simpler design methodology with high noise margins and robust characteristics to the device sizing, process variations, and temperature. Circuit design principles of the proposed ALSCL circuits are described, and performance analysis of various implementations is evaluated. The proposed logic circuit structure performance is tested using 0.18 µm technology with extensive simulations. The proposed logic family has simpler routing requirements compared to classical source-coupled circuits. The proposed circuit structure is functional without fine adjustment of the device sizing and the performance can be tuned by the bias current of the circuits, providing a wide range of performance characteristics with the trade-off for power consumption.

Cost effective Tanh activation function circuits based on fast piecewise linear logic

In this paper, an approximate 16-bit non-linear Tanh function circuit design is proposed for activation function in neural networks and digital signal processing, which is based on piecewise linear calculation. By sacrificing acceptable accuracy in computation, the proposed logic circuit structure can furtherly improve the overall performance of the design, with marked reduction in delay, area and power consumption. Linear calculation segments with simple shift-and-add logic architectures are adopted for easy hardware implementation. Additionally, tailored bias tuning and approximate accumulator design make a fine balance between complexity and error distribution. The mean absolute error (MAE) of the entire design is 0.0049. Compared with other state-of-art works in 90 nm CMOS process, the area of the circuit is 582μm2, and the energy is 0.0996 mW/GHz at 0.71 GHz. Moreover, the area-delay product is reduced by over 79.7% and the energy-delay product is reduced by over 42.4%. In the evaluation of its suitability in large applications, the accurate Tanh circuit and the proposed Tanh circuit are adopted in two neural networks to classify the Fashion-MNIST data and emotional EEG data. When the model converges, the accuracies of the test set only differs with a maximum of 0.2% and 0.3%.

A new analytical modelling of 10 nm negative capacitance-double gate TFET with improved cross talk and miller effects in digital circuit applications

In this paper, the workability of a Negative Capacitance (NC)-Double Gate (DG) Tunnel FET (NC-DGTFET) for digital logic circuit implementation has been detailed. New analytical modelling of the drain current of the NC-DGTEFT considering the band to band tunneling (BTBT), Band tail tunneling (BTT) and Source drain tunneling (SDT) have been investigated. Significant IOÑ0.025 μA/μm at 250 mV and SS∼12mv/dec - 22mv/dec with very low IOFF (∼fA/μm) is observed with the optimized device. SILVACO ATLAS and MATLAB have been used to validate the proposed model. The modeled NC-DGTFET based Inverter, NAND/NOR has been implemented and the power, delay propagation, and the power delay product (PDP) of the circuit have been analyzed to show the energy efficacy of the NC-DGTFET in the sub-threshold regime (STR) with respect to baseline TFET (B-TFET). To evaluate the impact of the Miller's effects on the digital performances, NC-DGTFET-based five stages Inverter with Fanout = 1 is considered a device under test (DUT) here. Peak overshoot voltage and delay for different fanout and ferroelectric thickness are detailed to show the efficacy of the proposed logic circuits in sub-threshold regime. Both the cross talk and the Miller effects are mitigated significantly in the NC-DGTFET-based digital circuits.

Performance analysis of 4-bit ternary adder and multiplier using CNTFET for high speed arithmetic circuits

Multiple valued logic (MVL) can represent an exponentially higher number of data/information compared to the binary logic for the same number of logic bits. Compared to the conventional devices, the emerging device technologies such as Graphene Nano Ribbon Field Effect Transistor (GNRFET) and carbon nanotube field effect transistor (CNTFET) appears to be very promising for designing MVL logic gates and arithmetic circuits due to some exceptional electrical properties such as the ability to control the threshold voltage. This variation of the threshold voltage is one of the prescribed techniques to achieve multiple voltage levels to implement the MVL circuit.This work presents a 4-input ternary adder using carbon nanotube field effect transistor (CNTFET). Many researchers have been done work on implementation of ternary adders and multipliers. But no one has done the comparison of this proposed ternary adder with different types of nano transistors. Hence this work has been proposed a design of low power and high speed 4-input adder which will be useful for designing of fast ternary multipliers. All the proposed designs have been simulated using emerging device such as CNTFET at 32nm technology node. From the simulations, we have calculated the power consumptions of the proposed designs, carry propagation delay and power delay product for the CNTFET circuits. It has been observed that CNTFET based proposed logic circuits given a better performance than the conventional logical circuits.

Hybrid Spintronics/CMOS Logic Circuits Using All-Optical-Enabled Magnetic Tunnel Junction

Spintronics is one of the emerging fields for next-generation low power, high endurance, non-volatile, and area efficient memory technology. Spin torque transfer (STT), spin orbit torque (SOT), and electric field assisted switching mechanisms have been used to switch magnetization in various spintronic devices. However, their operation speed is fundamentally limited by the spin precession time that typically ranges in 10–400 ps. Such a time constraint severely limits the possible operation of these devices in high-speed systems. Optical switching using ultrashort laser pulses, on the other hand, is able to achieve sub-picosecond switching operation in magnetic tunnel junctions (MTJs). In this paper, all optically switched (AOS) MTJ has been used to design high speed and low power hybrid MTJ/CMOS based logic circuits such as AND/NAND, XOR/XNOR, and full adder. Owing to the ultra-fast switching operation of AOS-MTJ, the circuit level results show that the energy and speed of AOS-MTJ based logic circuits are improved by 85% and 97%, respectively, when compared to STT based circuits. In comparison to SOT based designs, the proposed logic circuits show 10% and 91% improvement in energy efficiency and speed, respectively.

DGFinSAL: A New Low Power Adiabatic FinFET-Based Logic Family for DPA-Resistant Applications

In this paper, a novel low power, adiabatic, DPA-resistant logic family based on double-gate FinFET transistors is presented. Internet-of-Things devices have gained many applications in all aspects of human life. Therefore, the security and energy efficiency of such device is very important. Radio-frequency identification tags and wireless sensor networks use AES modules to encrypt secret information. Attackers have successfully tampered these modules using differential power analysis (DPA) attacks. Therefore, DPA-resistant circuits with high immunity are desirable. The proposed logic circuit family has been simulated using HSPICE and PTM 20 nm technology parameters. Simulation results show that the proposed logic circuits consume lower power up to 40% in comparison with the previous designs. Furthermore, the security of the proposed logic is evaluated using an 8-bit SBOX as a test bench circuit. It has been shown that the proposed design is immune to a DPA, through simulated attacks using Cadence Virtuoso and MATLAB software.

Memristive self-learning logic circuit with application to encoder and decoder

Different logic circuits based on memristors have been extensively investigated. However, most of these circuits require accurate initialization. A self-learning logic circuit based on mermristors that can achieve various logic gates without initialization is proposed in this paper. Three functional blocks, including a sum block, a learning block, and a compare block, are elaborately designed in the proposed logic circuit. Programmable switches in the sum and compare blocks enable the circuit to perform various logic gates, such as Boolean, IMPLY, and random logical combinations. In these various logical operations, the learning block can automatically obtain different memristance states. The aforementioned logic operations can easily be extended to multi-fan-in logic and logical cascade operations. Circuit designs of an encoder and decoder are considered as application examples. Finally, PSpice simulation results of the logic circuits and extended applications are provided. Simulation results indicate that the proposed circuit can effectively perform different logic operations and exhibits excellent robustness to circuit device variations.

Low power noise immune node voltage comparison keeper design for high speed architectures

The demand for high speed and area minimization has directed the designers towards dynamic CMOS logic design. The domino logic is one of the famous logic in dynamic CMOS logic. The designer needs to compromise the circuit speed and power consumption to reduce the impact of noise in domino logic circuit design. In this work, low power domino logic circuit is proposed to decrease power consumption with improvement in noise immunity. The low power consumption is achieved at the cost small sacrifice in delay. However, the proposed logic circuit has attained better Power Delay Product (PDP) as compared to existing noise tolerant circuits. The experimental simulation results shows the proposed logic exhibit 3.4% power reduction when compared with the low power domino logic circuit [10] for two input OR gates. The proposed logic had a little compromise with delay in the existing logics. However, the Power Delay Product (PDP) of proposed logic circuit has reduced as compared to existing techniques. The proposed logic also provides the better improvement in noise immunity parameters such as UNG and ANTE as compared to the existing logics. The proposed logic circuit based application circuit such as 4:1 multiplexer also provides better improvement in case of power consumption and noise immunity.

Implementation of Unbalanced Ternary Logic Gates with the Combination of Spintronic Memristor and CMOS

A memristor is a nanoscale electronic element that displays a threshold property, non-volatility, and variable conductivity. Its composite circuits are promising for the implementation of intelligence computation, especially for logic operations. In this paper, a flexible logic circuit composed of a spintronic memristor and complementary metal-oxide-semiconductor (CMOS) switches is proposed for the implementation of the basic unbalanced ternary logic gates, including the NAND, NOR, AND, and OR gates. Meanwhile, due to the participation of the memristor and CMOS, the proposed circuit has advantages in terms of non-volatility and load capacity. Furthermore, the input and output of the proposed logic are both constant voltages without signal degradation. All these three merits make the proposed circuit capable of realizing the cascaded logic functions. In order to demonstrate the validity and effectiveness of the entire work, series circuit simulations were carried out. The experimental results indicated that the proposed logic circuit has the potential to realize almost all basic ternary logic gates, and even some more complicated cascaded logic functions with a compact circuit construction, high efficiency, and good robustness.

Ultracompact and Low-Power Logic Circuits via Workfunction Engineering

An extensive analysis of sub-10-nm logic building blocks utilizing ultracompact logic gates based on recently proposed gate workfunction engineering (WFE) approach is provided. WFE sets the WF in the contacts as well as two independent gates of an ambipolar Schottky-barrier (SB) FinFET to alter the threshold of two channels, as a unique leverage to modify the logic functionality out of a single transistor. Thus, a single transistor (1T) CMOS pass-gate, 2T NAND and NOR gates as well as 3T or 4T XOR gates with substantial reduction in overall area (50%) and power (up to $\times 10$ ) dissipation can be implemented. To harness this potential and illustrate the capabilities of these compact ambipolar transistors, novel logic building blocks, including 6T multiplexer, 8T full-adder, 4T latch, 6T D-type flip-flop, and 4T AND-OR-invert (AOI) gates, are developed. Besides the logic verification using 7-nm devices, the dynamic performance of the proposed logic circuits is also analyzed. The comparative simulation study shows that WFE in independent-gate SB-FinFETs can lead to absolutely minimalist CMOS logic blocks without significant degradation to overall power-delay product (PDP) performance.

Ultra Low Power Adiabatic Logic Using Diode Connected DC Biased PFAL Logic

With the continuous scaling down of technology in the field of integrated circuit design, low power dissipation has become one of the primary focuses of the research. With the increasing demand for low power devices, adiabatic logic gates prove to be an effective solution. This paper briefs on different adiabatic logic families such as ECRL (Efficient Charge Recovery Logic), 2N-2N2P and PFAL (Positive Feedback Adiabatic Logic), and presents a new proposed circuit based on the PFAL logic circuit. The aim of this paper is to simulate various logic gates using PFAL logic circuits and with the proposed logic circuit, and hence to compare the effectiveness in terms of average power dissipation and delay at different frequencies. This paper further presents implementation of C17 and C432 benchmark circuits, using the proposed logic circuit and the conventional PFAL logic circuit to compare effectiveness of the proposed logic circuit in terms of average power dissipation at different frequencies. All simulations are carried out by using HSPICE Simulator at 65 nm technology at different frequency ranges. Finally, average power dissipation characteristics are plotted with the help of graphs, and comparisons are made between PFAL logic family and new proposed PFAL logic family.

Towards the design of hybrid QCA tiles targeting high fault tolerance

The increasing fabrication cost of CMOS-based computing devices and the ever-approaching limits of their fabrication have led to the search for feasible options with high device density and low power waste. Quantum-dot cellular automata (QCA) is an emerging technology with such potential to match the design target beyond the limits of state-of-the-art CMOS. But nanotechnologies, like QCA are extremely susceptible to various forms of flaws and variations during fabrication at nano scale. Thus, the exploration of ingenious fault tolerant structure around QCA is gaining high importance. This work targets a new robust QCA tile structure hybridizing rotated and non-rotated cell together resulting lesser kink energy. Different QCA logic primitives (majority/minority logic, fanout tiles, etc.) are made using such hybrid cell structure. The functional characterization using the kink energy and the polarization level of such QCA structures under different cell defects have been thoroughly investigated. The results suggest that the proposed QCA logic primitives have achieved high fault tolerance of 97.43 %. Also, 100 % fault tolerance can be ascertained if the proposed logic circuit drives the correct output with the application of $$\langle $$?001, 011$$\rangle $$? as a primitive test vector only. A comparative performance of the proposed logic over existing structure makes it more reliable.

A novel Voltage-mode CMOS quaternary logic design

This brief presents a novel kind of voltage-mode CMOS design that uses multiple threshold voltage transistors and three power supply lines to implement quaternary logic gates, showing lower power dissipation and using less area than the present voltage-mode quaternary circuits. Inverter, NMIN, and NMAX gates are simulated with the Spice tool using TSMC 0.18-/spl mu/m technology. The proposed logic circuits overcome the limitations of previous implementations used for multiple-valued logic circuits, such as static power consumption and noise vulnerability.

Extended phase-mode logic-circuits with resistive ground contact

We present extended phase-mode logic (EPL) circuits which have resistive ground contact. The phase-mode logic utilizes magnetic flux-transfer and is based on pulse propagation, i.e., it is one of single flux quantum systems. The proposed logic circuits of the EPL family can have the same ground reference, contrary to the original phase-mode circuits, Therefore, it is possible to couple different EPL elements on a single ground reference. Basic components of the EPL family (a phase-conserving branch, a phase-distributing branch, and an INHIBIT gate controlled by fluxon) are presented. The phase-distributing branch and the INHIBIT gate have been fabricated using a Nb/AlO/sub x//Nb Josephson-junction technology and tested. A fan-in operation of the phase-distributing branch and the first full operation of the INHIBIT gate are successfully demonstrated. As an example of the EPL logic circuits consisting of plural gates on a single ground reference, a simulation of a 2-bit full adder circuit is also presented. >