High Performance Energy-Efficient Leakage-Tolerant Dual Keeper Pseudo Domino Logic

Abstract

In this paper, an improved high performance energy-efficient leakage-tolerant dual keeper pseudo domino logic circuit is proposed. Circuit design methodologies such as pseudo domino, stacking effect and inverted clock-controlled dual keeper are used in the proposed work for significant reduction of the circuit’s propagation delay and leakage current. Using pseudo-domino logic voltage swing at the output is reduced, stacking effect reduces the leakage current and charge sharing issues in the circuit are reduced by an inverted clock-controlled dual keeper circuit. Leakage current in the proposed circuit is decreased by 21.9%, 20.8%, 71.6%, 52.4% and 57.5% to the conventional logic, DOIND logic, DVT DOIND logic, DFD logic and C3D domino logic, respectively at a 27°C temperature and 1GHz clock frequency. Similarly, delay in the proposed circuit is reduced by 83.3%, 80.1%, 89.8%, 81.3% and 81.5% in comparison to conventional logic, DOIND logic, DVT DOIND logic, DFD logic and C3D domino logic circuit, respectively. Performance metrics like power dissipation, delay, PDP, leakage current, static power, and EDP of the proposed circuit are analysed and compared with the existing domino logics. Monte-Carlo simulation is performed using 1000 samples to analyse the performance of the proposed circuit. The proposed logic circuit is also tested against temperature and process variations. The median values of the proposed buffer circuit’s power and delay are 5.6µW and 1.28ps, respectively and the standard deviation of average power and propagation delay are 633.62nW and 84.37fs, respectively at 27°C and 1GHz clock frequency.