Comparative Analysis Domino Logic Based Techniques For VLSI Circuit

Shilpa Kamde,Pratik Hajare,Jitesh Shinde,Sanjay Badjate

doi:10.24297/ijct.v12i8.2998

Abstract

Domino logic is a CMOS-based evolution of the dynamic logicÂ techniques Â basedÂ onÂ eitherÂ PMOSÂ orÂ NMOS transistors. Domino logic technique is widely used in modern digital VLSI circuit. Dynamic logic is twice as fast as static CMOS logic because it uses only N fast transistors. The Dynamic (Domino) logic circuit are often favored in high performance designs because of the high speed and low area advantage.Four different dynamic circuit techniques including Basic domino logic circuit are compared in this paper for low power consumption and speed of domino logic circuits. For digital circuit simulation used BSIM(Berkeley Short Channel IGFET ) Model because it control leakage current.

Highlights

To achieve low power and speed different size of transistor and supply voltages are scaled down along with different technology
Domino logic circuit techniques are extensively applied in high performance microprocessors due to the superior speed and area characteristics of domino CMOS circuits as compared to static CMOS circuits [1]-[2]
The comparative analysis showed the maximum number of input for OR gate low swing domino with fully driven keeper [LSDFDK] technique is better because it had low power consumption, low propagation delay but domino logic with keeper had less power delay product (PDP)

Summary

INTRODUCTION

To achieve low power and speed different size of transistor and supply voltages are scaled down along with different technology. The High speed and leakage Tolerant Domino Technique add a footer transistor that is initially OFF in the evaluation phase to reduce leakage and turned ON to complete the evaluation. In order to avoid the delay penalty due to an initially OFF footer transistor, an extra path for evaluation is provided that is controlled by the output[4]. This technique reduce the contention current between keeper transistor and NMOS transistor in evaluation phase. This circuit increase speed and decreases the power dissipation of the circuit as compared to other domino logic styles. The voltage swings at the nodes of domino logic circuits are modified.[11]

Basic Domino Logic

Domino Logic Circuit with keeper

High Speed Leakage Tolerant Domino

Low Swing Domino Logic

CONCLUSION