Keeper topology for optimization of power delay product

Abstract

Dynamic domino logic circuits are widely used in modern digital VLSI circuits. These dynamic circuits are often favored in high performance designs because of the speed advantage offered over static CMOS logic circuits. The main drawbacks of dynamic logic are lack of design automation and less tolerance to noise. In performance-critical applications, Domino logic is widely employed since it has a lower delay at the cost of reduced noise immunity, compared with static CMOS logic but still it is not preferred much for practical applications mainly due to delay variations and large power dissipation. In this work, a new circuit technique based on keeper topology is presented for simultaneously reducing power consumption and delay variation thereby enhancing evaluation speed and noise immunity in deep submicron technology (DSM). The proposed technique modifies the Single Vt domino logic circuit with keeper. Ground, power supply and threshold voltages are simultaneously optimized to minimize the power delay product (PDP). The proposed techniques are compared by performing detailed transistor simulations on benchmark circuits such as two input OR gate and three input AND gate using Micro wind 3 and DSCH3 CMOS layout CAD tools.