A novel Voltage-mode CMOS quaternary logic design

Abstract

This brief presents a novel kind of voltage-mode CMOS design that uses multiple threshold voltage transistors and three power supply lines to implement quaternary logic gates, showing lower power dissipation and using less area than the present voltage-mode quaternary circuits. Inverter, NMIN, and NMAX gates are simulated with the Spice tool using TSMC 0.18-/spl mu/m technology. The proposed logic circuits overcome the limitations of previous implementations used for multiple-valued logic circuits, such as static power consumption and noise vulnerability.