The design of low power multiple-valued logic encoder and decoder circuits

I.M Thoidis,A Thanailakis,I Karafyllidis,D Soudris

doi:10.1109/icecs.1999.814484

The design of low power multiple-valued logic encoder and decoder circuits

I.M Thoidis, A Thanailakis + Show 2 more

https://doi.org/10.1109/icecs.1999.814484

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Publication Date: Sep 5, 1999

Citations: 14

Affiliation: Democritus University of Thrace

#Decoder Circuits #Encoder Circuits + Show 8 more

Abstract
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Abstract

Novel multiple-valued logic (MVL) voltage-mode circuits, namely encoder and decoder circuits, using both enhancement- and depletion-mode MOSFETs, are introduced. High performance and low power dissipation, due to zero-static power consumption during their steady-state operation, characterize the proposed circuits. More specifically, considering quaternary logic, and 0.7 /spl mu/m technology, the encoder and decoder circuits are implemented and simulated by the SPICE tool. The results obtained show substantial improvements, in terms of power, speed, and transistor count, compared with existing designs.

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