Ultracompact and Low-Power Logic Circuits via Workfunction Engineering

Talha F Canan,Avinash Karanth,Ahmed Louri,Savas Kaya

doi:10.1109/jxcdc.2019.2962494

Abstract

An extensive analysis of sub-10-nm logic building blocks utilizing ultracompact logic gates based on recently proposed gate workfunction engineering (WFE) approach is provided. WFE sets the WF in the contacts as well as two independent gates of an ambipolar Schottky-barrier (SB) FinFET to alter the threshold of two channels, as a unique leverage to modify the logic functionality out of a single transistor. Thus, a single transistor (1T) CMOS pass-gate, 2T NAND and NOR gates as well as 3T or 4T XOR gates with substantial reduction in overall area (50%) and power (up to $\times 10$ ) dissipation can be implemented. To harness this potential and illustrate the capabilities of these compact ambipolar transistors, novel logic building blocks, including 6T multiplexer, 8T full-adder, 4T latch, 6T D-type flip-flop, and 4T AND-OR-invert (AOI) gates, are developed. Besides the logic verification using 7-nm devices, the dynamic performance of the proposed logic circuits is also analyzed. The comparative simulation study shows that WFE in independent-gate SB-FinFETs can lead to absolutely minimalist CMOS logic blocks without significant degradation to overall power-delay product (PDP) performance.

Highlights

A S silicon-based CMOS technology is searching for alternative devices and approaches to extend its dominance and to delay the imminent demise of Moore’s scaling, minimal changes to the established FinFET architecture is still welcomed due to the associated cost savings and rapid adaption cycle [1], [2]
The workfunction engineering (WFE) is selectively applied to Schottky-barrier (SB) FinFETs with independent gate inputs, which leads to entirely novel logic elements such as single transistor (1T) CMOS pass-gates as well as 3T/4T XOR gates and 2T NAND/NOR gates with noninverting inputs
In order to serve as baselines for performance comparison, we provide in this table two alternative AOI implementations: one with a three-stage design based on separate and, or, and inverter gates utilizing WFE and one implemented as a compact one-stage static-CMOS counterpart with standard p-n junction FinFETs

Summary

Introduction

A S silicon-based CMOS technology is searching for alternative devices and approaches to extend its dominance and to delay the imminent demise of Moore’s scaling, minimal changes to the established FinFET architecture is still welcomed due to the associated cost savings and rapid adaption cycle [1], [2]. Less revolutionary, this ‘‘more-of-Moore’’ approach can provide additional time for the paradigm-shifting alternatives to Si CMOS to be developed fully [3]. We illustrate how the compact gate designs based on ambipolar SB-FinFETs in sub-10 nm can be conveniently utilized to build novel logic elements that have never been explored before

Objectives

Findings

Discussion

Conclusion