Abstract
A comprehensive simulation study has been conducted to show fine-grain reconfigurability in CMOS circuits using work-function engineering (WFE) on Schottky Barrier (SB) FinFETs for sub-10nm gate length. The study has three subsections. First, two-transistor (2T) & 4T AOI (and-or-invert)/ OAI (or-and-invert) gates with select bits that allow multiple logic functions are introduced. Secondly, the use of WFE to create ultra-compact reconfigurable logic circuits of fundamental operations (0,1,OR, AND,NAND,NOR,XOR) are explored via novel 2T, 3T and 4T gates. These circuits include one or two select bits that are capable of commanding up to four functions with two inputs. To further illustrate the potential of WFE for reconfigurable logic, novel multi-stage circuits such as compact full-adders are also modelled via TCAD simulations. Power×delay product (PDP) figures and DC gain of the proposed gates are quantified and compared against the CMOS designs with similar functionality. Finally, we also design a novel compact one-bit arithmetic logic unit (ALU) which has seven exclusive logic operations (1, NAND, OR, XOR, NOR, Addition, Subtraction) with three select bits using only 26 SB-FinFETs, saving substantial amount of power and chip area. The trade-offs between the number of metal work-functions used in the designs, circuit complexity and simulated performance metrics are also provided. The comparative simulations between reconfigurable SB-FinFET based designs versus conventional p-n junction FinFET circuits show that WFE can lead to absolutely minimalist reconfigurable CMOS logic blocks using ×3 to ×10 less power and between ×2 and ×15 less area than static CMOS counterparts. Although they suffer greater delays (×2 to ×5), the overall PDP performance remains comparable to conventional CMOS.
Highlights
INTRODUCTIONBased on such relatively simple yet fundamental optimization of Schottky Barrier (SB)-FinFET thresholds via work-function engineering (WFE), we have been able to demonstrate minimalist 2T NOR/NAND/XOR gates and logic blocks (excluding inverted inputs of XORs), as explored in our recent works [12]
These savings translate into reduced power consumption and parasitics in these novel gates such that they possess Power×delay product (PDP) figures similar to the conventional FinFET counterparts, despite being slower in switching as independent gate configuration always lead to lower transconductance
The merit of work-function engineering as applied to SBFinFETs to achieve fine-grain reconfigurability is explored with basic one-stage and multi-stage circuits
Summary
Based on such relatively simple yet fundamental optimization of SB-FinFET thresholds via WFE, we have been able to demonstrate minimalist 2T NOR/NAND/XOR gates and logic blocks (excluding inverted inputs of XORs), as explored in our recent works [12] These static CMOS gates are briefly reintroduced in Fig., along with their logic characteristics obtained via TCAD simulations. They illustrate that by assigning a maximum of two or three work-functions in the SB-contacts and gate metals of FinFETs, it is possible to design absolutely smallest logic gates in terms of transistor counts and area These savings translate into reduced power consumption and parasitics in these novel gates such that they possess PDP figures similar to the conventional FinFET counterparts, despite being slower in switching as independent gate configuration always lead to lower transconductance (gm). These reconfigurability will be key to developing novel ultra-compact and low power circuitry in hardware security with logic-locking capabilities
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More From: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
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