poly-Si Thin-film Transistors Research Articles

New Low-Frame-Rate Compensating Pixel Circuit Based on Low-Temperature Poly-Si and Oxide TFTs for High-Pixel-Density Portable AMOLED Displays.

A new low-frame-rate active-matrix organic light-emitting diode (AMOLED) pixel circuit with low-temperature poly-Si and oxide (LTPO) thin-film transistors (TFTs) for portable displays with high pixel density is reported. The proposed pixel circuit has the excellent ability to compensate for the threshold voltage variation of the driving TFT (ΔVTH_DTFT). By the results of simulation based on a fabricated LTPS TFT and a-IZTO TFT, we found that the error rates of the OLED current were all lower than 2.71% over the range of input data voltages when ΔVTH_DTFT = ±0.33 V, and a low frame rate of 1 Hz could be achieved with no flicker phenomenon. Moreover, with only one capacitor and two signal lines in the pixel circuit, a high pixel density and narrow bezel are expected to be realized. We revealed that the proposed 7T1C pixel circuit with low driving voltage and low frame rate is suitable for portable displays.

Highly Sensitive Temperature Sensor Using Low-Temperature Polysilicon Oxide Thin-Film Transistors

We report highly sensitive temperature sensing circuits using low temperature polysilicon oxide (LTPO) thin-film transistors (TFTs) on a glass substrate. The sensor has the LTPO operational amplifier (Op-Amp) made of dual gate (DG) amorphous InGaZnO (a-IGZO) and low temperature poly-Si (LTPS) TFTs by blue laser annealing process. The DG a-IGZO TFTs-based sensing circuit exhibits a sensitivity of 37.9±3 mV/°C and it can be further boosted to 223.33±8 mV/°C by incorporating LTPO Op-Amp for body temperature detection (35~40 °C). The DG a-IGZO TFT exhibits robust threshold voltage stability ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta {\rm V}_{Th}$ </tex-math></inline-formula> = −0.16 V) with temperature, which is essential for the practical development of the proposed LTPO differential temperature sensor (TS) to accurately measure the human body temperature.

Gate Voltage Pulse Rising Edge Dependent Dynamic Hot Carrier Degradation in Poly-Si Thin-Film Transistors

Dynamic degradation becomes a critical issue for thin-film transistors (TFTs) used in emerging new displays driven by high frequency gate voltage ${V}_{\text {G}}$ pulses. In this study, ${V}_{\text {G}}$ pulse rising edge dependent dynamic hot carrier degradation of poly-Si TFTs is investigated. It is demonstrated that rising edge of ${V}_{\text {G}}$ pulses which swing within the OFF-state of TFTs causes the degradation, while that of normal ${V}_{\text {G}}$ pulses which switch between the ON and OFF states across the flat band voltage ${V}_{\text {FB}}$ of TFTs does not. Based on transient TCAD simulation, the underlying mechanism of rising edge dependent degradation is proposed, which is based on the non-equilibrium PN junction degradation model previously proposed to explain ${V}_{\text {G}}$ pulse falling edge dependent degradation of poly-Si TFTs. Hence, the dynamic degradation model of poly-Si TFTs related to both rising and falling edge of the ${V}_{\text {G}}$ pulses can be unified now, which is applicable to fast gate pulses with steep rising and/or falling edges in sub- $\mu \text{s}$ level.

Degradation and Failure of Flexible Low-Temperature Poly-Si TFTs Under Dynamic Stretch Stress

Degradation and failure behaviors of the flexible low-temperature poly-Si (LTPS) thin film transistors (TFTs) under repetitive stretch stress parallel to channel length (L) direction are investigated. A geometric effect is observed in degradation of the threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ), which depends on the channel width (W) and active area ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">WL</i> ), while has a weak correlation with L. Three failure modes of TFTs are identified from their I-V characteristics: damage in the gate insulator (GI), channel traps generation, and metal line cracks. Failure statistics show that the GI failure has a low failure rate and follows the exponential distribution, while the other two modes have high failure rates in the early stage of the stretch cycles, and their failure distributions follow the limited failure population (LFP) model.

Static and Radio-Frequency Characteristics of Green-Nanoseconds Laser-Crystallized Poly-Si Thin-Film Transistors

In this study, we investigate the static and radio-frequency characteristics of poly-Si thin-film transistors (TFTs) with the channels treated by using either green-nanoseconds laser crystallization (GLC) or solid phase crystallization (SPC) processes. The influences of the crystallization schemes on the granular structures of the resulted poly-Si as well as the device characteristics were studied and compared. Scanning Electron Microscope observations indicate that mean grain size of the 50 nm-thick poly-Si films is approximate 70 nm following the SPC process, whereas GLC process enlarges the mean grain size to 0.5 μm. As a consequence, GLC poly-Si TFTs exhibit greatly improved electron mobility and transconductance as compared to the SPC ones. Moreover, superior high-frequency characteristics with cut-off frequency (f T ) and maximum oscillation frequency (f max) of 21.1 GHz and 24.1 GHz, respectively, are recorded in GLC devices with channel length of 0.26 μm.

Deep UV Sensors Enabling Solar-Blind Flame Detectors for Large-Area Applications

Large-area compatible, solar-blind deep-ultraviolet sensors based on active pixels are demonstrated with CMOS amplifiers based on poly-Si thin-film transistors and Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> thin-film photoresistors. The active pixel configuration sensor enables approximately 40X higher responsivity compared to a discrete sensor, and the CMOS inverter amplifier exhibits a gain of 210 V/V. The Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> -based sensors were integrated on the same substrate depositing the films using magnetron sputtering at room temperature, ensuring its compatibility with large-area applications. The responsivity of discrete Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> sensors was evaluated at different wavelengths in the deep-ultraviolet and visible ranges, and showed a maximum responsivity of 51 A/W for a wavelength of 232 nm, with a deep-ultraviolet to visible light rejection ratio of approximately 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The active pixel sensor was implemented as flame detector resulting in an output voltage signal of up to 2 V when the system was exposed to a flame under regular background illumination conditions.

Raised Source/Drain (RSD) and Vertical Lightly Doped Drain (LDD) Poly-Si Thin-Film Transistor

The raised source/drain (RSD) structure is one of thin film transistor designs that is often used to improve device characteristics. Many studies have mentioned that the high impact ionization rate occurring at a drain side can be reduced, owing to a raised source/drain area that can disperse the drain electric field. In this study, we will discuss how the electric field at the drain side of an RSD device is reduced by a vertical lightly doped drain (LDD) scheme rather than a RSD structure. We used different raised source/drain forms to simulate the drain side electric field for each device, as well as their output characteristics, using Integrated Systems Engineering (ISE-TCAD) simulators. Different source and drain thicknesses and doping profiles were applied to verify the RSD mechanism. We found that the electric fields of a traditional device and uniform doping RSD structures are almost the same (~2.9 × 105 V/cm). The maximum drain electric field could be reduced to ~2 × 105 V/cm if a vertical lightly doped drain RSD scheme was adopted. A pure raised source/drain structure did not benefit the device characteristics if a vertical lightly doped drain design was not included in the raised source/drain areas.

LTPS TFTs with an Amorphous Silicon Buffer Layer and Source/Drain Extension

A low leakage poly-Si thin film transistor (TFT) is proposed featuring hydrogenated amorphous silicon (a-Si:H) buffer layer and source/drain extension (SDE) by using technology computer aided design (TCAD) simulation. This architecture reduces off-current effectively by suppressing two leakage current generation mechanisms with little on-current loss. The amorphous silicon buffer layer having large bandgap energy (Eg) suppresses both thermal generation and minimum leakage current, which leads to higher on/off current ratio. In addition, the formation of lightly doped region near the drain alleviates the field-enhanced generation in the off-state by reducing electric field. TCAD simulation results show that the proposed TFT shows more than three orders of magnitude lower off-current than low-temperature polycrystalline silicon (LTPS) TFTs, while maintaining on-current.

Parameter Extraction Using the Output Characteristics of Thin-Film Transistors in Weak-Conduction and Triode-Region

A novel method for the parameter extraction of thin-film transistors in weak-conduction and triode-region is presented. The parameter extraction is performed using two different and consistent functions based on the integration of experimental output characteristic. The method was tested using measured data of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) and the results were compared with previously reported conventional methods.

Improvement of negative bias temperature instability of LTPS TFTs by high pressure H2O annealing

In this study, high pressure H2O annealing (HPA) was performed to improve the reliability of low temperature poly-Si thin film transistors (LTPS TFTs) fabricated on a polyimide (PI) substrate. Due to the low heat resistance of the PI substrate, the pressure was high to reduce the temperature of the heat treatment. HPA was performed at 130 °C and 0.3 Mpa in an H2O ambient for 2 h. After HPA treatment, the threshold voltage (VT) shifted to the positive direction from −2.27 V to −1.75 V, and the hysteresis (ΔVT) decreased from 0.67 V to 0.24 V. The density of states (DOS) measurement shows that the interface trap decreased after HPA processing, hence, it is assumed that stability for bias stress has improved. Before and after HPA, the VT shift for negative bias temperature instability (NBTI) stress was 1.19 V and 0.2 V, respectively. After HPA treatment, ΔVT decreased significantly for bias stress. It seems that the decomposed oxygen from H2O diffused to the gate insulator and combined with Si to reduce the oxygen vacancy. The strength of the gate insulator improved after HPA.

Characterization of selectively oriented polycrystalline silicon thin films formed by multiline beam continuous-wave laser lateral crystallization with overlapping

The uniformity of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) over a large scale is an important element in their application. Characteristics of poly-Si thin films are the key factors influencing the performance of TFTs. In this area, we developed void-free (100)-surface oriented poly-Si thin films over large areas using multiline beam continuous-wave laser lateral crystallization (MLB-CLC) with overlapping scanning. Predominantly (100)-surface oriented poly-Si thin films are formed over large areas with the laser power from 5 to 8 W. (100), and random, or (211)-surface orientations can be selected by varying the laser power and scanning speed. In addition, characterization of these selectively oriented poly-Si thin films is analyzed using two-dimensional X-ray diffraction and hard X-ray photoelectron spectroscopy.

Impacts of Stress Voltage and Channel Length on Hot-Carrier Characteristics of Tunnel Field-Effect Thin-Film Transistor

Hot-carrier stress (HCS) characteristics of polycrystalline-silicon (poly-Si) tunnel field-effect thin-film transistors are investigated and compared with the conventional poly-Si thin-film transistors (TFTs). After HCS with ${V}_{{\text {DS}}} = {2}{V}_{{\text {GS}}} = {20}$ V for 1000 s, poly-Si TFT exhibits significant ON-state current ( ${I}_{{\text {on}}}{)}$ degradation ~85% and two-step subthreshold swing (SS) behavior due to the serious lattice damage between the pinch-off point and the drain. For the poly-Si tunnel field-effect transistor (TFET), less ${I}_{{\text {on}}}$ degradation ~70% is observed. In addition, the stress drain voltage ( ${V}_{{\text {DS}}}$ ) effect of the HCS is also studied. When the stress ${V}_{{\text {DS}}}$ is increased from 10 to 15 V, the poly-Si TFETs exhibit more obvious stressed ${I}_{{\text {on}}}$ degradation (~24.4%) than that of poly-Si TFTs (~6.5%). When the stress ${V}_{{\text {DS}}}$ is further increased from 15 to 20 V, the poly-Si TFETs exhibit less stressed ${I}_{{\text {on}}}$ degradation (~62.4%) than that of poly-Si TFTs (~85%). Because the increase in the stress drain voltage is dropped in the pinch-off region of the poly-Si TFETs after the pinch-off phenomenon occurs, resulting in less impact on the stress field at the tunnel junction. When the channel length is decreased, the results show that the HCS effect of poly-Si TFETs is insensitive to the channel length, and the poly-Si TFTs show more serious electrical degradation and breakdown behavior with the scaling down of the channel length. The stronger HCS immunity of poly-Si TFETs would be an important advantage to replacing poly-Si TFTs for applications of 3-D integrated circuits.

Bias stress instability of LTPS TFTs on flexible substrate with activation annealing temperature

In this paper, we identified the defect state of p-channel low temperature poly-Si thin film transistors (LTPS TFTs) fabricated on a polyimide (PI) substrate that is distributed differently in the interface and channel areas depending on the activation annealing temperature, as well as observed the effect on the threshold voltage (VT) and reliability. To verify the effect of the process temperature on the performance of the LTPS TFTs, an activation heat treatment was conducted at 400 °C, 370 °C and 340 °C. More defects were distributed in the interface and channel area of LTPS TFTs with low heat treatment temperature, resulting in VT formed at a higher voltage. After the negative bias temperature instability (NBTI) test, the VT shifted in the negative voltage direction and moved −0.13 V, −0.51 V and −0.72 V from LTPS TFTs with high activation annealing temperature. In the hot carrier instability (HCI) test, VT also shifted to the negative direction of −0.19 V, −0.51 V, and −1.07 V. The defects distributed in the interface and channel areas that are not curated or activated due to the low activation annealing temperature caused instability under the bias stress.

Reversely-Synchronized-Stress-Induced Degradation in Polycrystalline Silicon Thin-Film Transistors and Its Suppression by a Bridged-Grain Structure

In this letter, a reversely synchronized stress (RSS) is proposed to simulate the working condition of switching thin-film transistors (TFTs) in active-matrix displays. The reliability of polycrystalline silicon (poly-Si) TFTs under RSS is characterized and investigated. RSS brings huge device degradation. A dynamic hot carrier (HC) effect, dependent on transition edges of RSS, dominates the degradation. Combined with a transient simulation, the degradation mechanism under RSS in poly-Si TFTs is discussed and developed. To suppress RSS-induced HC degradation, a bridged-grain (BG) structure is employed in the active layer of poly-Si TFTs. Via BG lines’ reducing the lateral electric field in the channel at source/drain sides, the reliability of BG TFTs under RSS is significantly improved.

Performance dependence of self-aligned dual-gate poly-Si TFTs on localized defective regions

This study investigates effects of localized defect regions on electrical characteristics of self-aligned dual-gate poly-Si thin-film transistors (TFTs). The thickness of the poly-Si channel layer ranges from 20 nm to 140 nm. The threshold voltage, subthreshold swing, and mobility are found to be sensitive to the defect position. The localized defects in the left channel (source side) exhibit a significant impact while those in the right channel (drain side) show a lower influence on the TFT performance. In addition, the performance variation caused by the localized defects in the right channel is highly sensitive to the magnitude of the applied drain bias. A higher drain bias can observably reduce the performance degradation. Effects of multiple defect regions on the electrical behavior of the TFTs are also explored. We found that the upper width of the defect regions dominates the TFT performance deterioration. The hole transport, hole concentration distributions, and current flowlines are analyzed to study the physical mechanisms.

Empirical noise performance of prototype active pixel arrays employing polycrystalline silicon thin-film transistors.

In the spirit of overcoming the signal-to-noise limitations of active matrix, flat-panel imagers (AMFPIs) which employ array circuits based on a-Si:H thin-film transistors (TFTs), an empirical investigation of the noise properties of prototype active pixel arrays based on polycrystalline silicon (poly-Si) TFTs is reported. Like a-Si:H, poly-Si supports fabrication of large area, monolithic x-ray imaging arrays and offers good radiation damage resistance, while providing electron and hole mobility orders of magnitude higher. Compared to pixel circuits typically consisting of a single addressing switch in an AMFPI array, the pixel circuit of an active pixel array includes an amplifier that magnifies the imaging signal prior to readout by external acquisition electronics. Also, while readout erases signal stored in the pixels for AMFPI arrays, active pixel arrays allow multiple nondestructive readout, which can be used to reduce noise. The prototype arrays investigated in this paper were developed to explore the effect of variation in amplifier design on noise. A pair of prototype arrays incorporating single-stage and two-stage poly-Si pixel amplifiers were examined. The arrays incorporate various amplifier designs in which dimensions of some of the three (or four) poly-Si TFTs per pixel circuit for the single-stage array, and some of the five poly-Si TFTs for the two-stage array, were varied. The arrays were operated using a recently developed electronic data acquisition system that allows variation of operational conditions such as voltages and timing of control signals. The arrays were operated in the absence of radiation in various correlated multiple sampling modes, with and without the injection of charge directly into the pixel circuits for measurements of in-pixel gain and pixel noise. Pixel noise, referred back to the input of the pixel amplifier, was compared to predictions generated by a sophisticated circuit simulation model. Across the various pixel circuit designs, the median in-pixel gain for the single-stage and two-stage arrays was measured to be ×9.3 and ×25, respectively. These gain levels were sufficient to reduce the contribution of external noise, defined as the electronic additive noise in the absence of noise contributions from circuitry in the pixel and referred back to the input of the pixel amplifier, to less than 340 e. As a result, median pixel noise results as low as ~695 e and 866 e, acquired using eight samples, were observed from the best-performing single-stage and two-stage designs, respectively. While the magnitude of pixel noise predicted by simulation was lower than the measured results, there was generally good agreement between simulation and measurement for the functional dependence of noise on operating voltages, timing, and sampling mode. The single-stage and two-stage arrays examined in this study demonstrated pixel noise well below that typically demonstrated by AMFPIs. Through proper design, it should be possible to maintain the noise levels observed in this study irrespective of the size and pitch of an active pixel array. Further reduction in pixel noise may be possible through more optimized pixel circuit design, faster readout, or improvements in fabrication.

Origin of Spontaneous Degradation of Flexible Poly-Si TFTs After Dynamic Bending

The origin of an abnormal spontaneous degradation of low-temperature polycrystalline Si (LTPS) thin-film transistors (TFTs) is investigated. After being subjected to dynamic bending stress, LTPS TFTs will continuously degrade when stored in a normal condition. Studies have shown that the interaction between the sensitive area of the TFTs and the O2 in ambient environment causes the spontaneous degradation. Defects at the gate oxide/channel interface generated by mechanical stress continuously capturing electrons with the help of oxygen is regarded as the origin of spontaneous degradation. In contrast, moisture in air can effectively suppress spontaneous degradation by reacting with the above defects to form relatively stable atom groups.

A Physical-Based Analytical Model for the Kink Current of Polycrystalline Silicon TFTs

A physical-based analytical kink current model for polycrystalline -silicon (poly-Si) thin-film transistors (TFTs) has been proposed. Two important mechanisms for the kink current, namely carrier impact ionization and the parasitic bipolar junction transistor effect, are physically included in the model without introducing any artificial parameters. The proposed kink current model is fully compatible with existing ON-state drain current models of poly-Si TFTs. Model parameter extraction procedure is presented, which is based on a group of output characteristics of poly-Si TFTs with different channel lengths. The model prediction straightforwardly calculated with a set of extracted parameters is verified by excellent agreement with experimental output characteristics measured from TFTs over a range of channel lengths and gate voltages.

Optimized Design of Carrier Injection Terminal for Reliable Low-Temperature Poly-Si TFTs Under Dynamic Hot-Carrier Stress

Dynamic hot-carrier (HC) degradation can be effectively suppressed in four-terminal low-temperature poly-Si (LTPS) thin film transistors (TFTs) with a carrier injection terminal. In order to enhance the reliability of the four-terminal LTPS TFTs, geometry effect of the carrier injection terminal, such as width and location, on the dynamic HC degradation is systematically studied. It shows that a wider carrier injection terminal, which provides more carriers injection, can suppress the degradation more effectively. As for the location, if the injection terminal is adjacent to the edge of the drain depletion region, which extends into the channel at the falling time of the gate voltage pulses, the four-terminal TFTs can provide the best immunity to the dynamic HC degradation. The proposed optimization scheme can greatly enhance the reliability of LTPS TFTs, and the mechanism can be understood based on the nonequilibrium p-n junction degradation model.

A Unique Approach to Generate Self-Aligned T-Gate Transistors in Counter-Doped Poly-Si With High Etching Selectivity and Isotropy

A unique approach for fabricating poly-Si thin-film transistors (TFTs) with self-aligned T-shaped gate (T-gate) structure is reported. A counter-doped poly-Si process comprises an in-situ doped ${n}^{+}$ poly-Si deposition followed by a subsequentshallow implantation of BF $_{{2}}^{+}$ . Both high etching isotropy in ${n}^{+}$ poly-Si and high etching selectivity between ${n}^{+}$ poly-Si and B-doped poly-Si in a Cl2-based plasma process are the key enablers for the fabrication of our T-gate structures. Thanks to good control in the shape and deformation of our T-gate structure, sidewall air-gap spacers in combination with self-aligned Ni silicided gate and source/drain were established. High-performance sub-micron poly-Si TFTs are evidenced by superior transfer characteristics measured on TFTs with effective gate length of $0.15~\mu \text{m}$ . The unique T-gate structure provides an effective way for possible production of poly-Si radio-frequency TFTs viable for emerging new applications.