poly-Si Thin-film Transistors Research Articles

Dynamic-Gate-Stress-Induced Degradation in Bridged-Grain Polycrystalline Silicon Thin-Film Transistors

In this paper, degradation behaviors of bridged-grain (BG) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) are systematically characterized and investigated. Device degradation exhibits a two-stage behavior, which is related to pulse falling time ( $t_{f}$ ). A faster $t_{f}$ brings a larger ON-current ( $I_{\mathrm{\scriptscriptstyle ON}}$ ) increase in the first stage and a larger $I_{\mathrm{\scriptscriptstyle ON}}$ decrease in the second stage. Electron trapping/injection into gate oxide and dynamic hot carrier effect are found to be responsible to $I_{\mathrm{\scriptscriptstyle ON}}$ increase in the first stage and $I_{\mathrm{\scriptscriptstyle ON}}$ decrease in the second stage, respectively. Compared with normal poly-Si TFTs, BG poly-Si TFTs show much more reliable performance under the same dynamic gate stress. The larger $I_{\mathrm{\scriptscriptstyle ON}}$ increase in the first stage in BG poly-Si TFTs is attributed to the enhanced vertical electric field in the channel near the gate oxide, while the much smaller $I_{\mathrm{\scriptscriptstyle ON}}$ decrease in the second stage is attributed to lateral electric field reduction caused by the sharing of the field across multiple reversely biased junctions inside the active channel. Incorporated with transient simulations, the degradation mechanisms for both the first stage and the second stage are elucidated. In addition, the impact of the first-stage degradation on the second-stage degradation is also clarified.

Advanced Four-Mask Process Bottom-Gate Poly-Si TFT via Self-Aligned NiSi2Seed-Induced Lateral Crystallization

We report on a method to fabricate high-performance bottom-gate poly-Si (BGPS) thin-film transistors (TFTs) with a four-mask process via self-aligned (SA) NiSi2 seed-induced lateral crystallization (SILC). Previously, the BGPS TFT crystallized by SILC was reported to have high electrical performance with a simple process. However, this approach still requires an additional mask for lateral crystallization, making the process more complicated and expensive. In this letter, by using the SA-SILC method, only a few NiSi2 seeds reach the intrinsic Si surface through the side edges of the etch stopper and then crystallize the channel. This SA-SILC enables low metal contamination by a few seeds in the channel, shorter annealing time due to reduced length for SILC, and a simple four-mask process. The SA-SILC BGPS TFTs exhibited a steep subthreshold slope of 0.16 Vdecade $^{\mathrm { {-1}}}$ , a high field-effect mobility of 230 cm $^{2}\text{V}^{-1}\text{s}^{-1}$ , and kink-free output characteristics.

Extended-Gate pH Sensors Using Self-Aligned Four-Terminal Metal Double-Gate Low-Temperature Polycrystalline-Silicon Thin-Film Transistors on Glass Substrate

High-performance polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) on glass substrate are applicable to high-performance and low-cost pH sensors. We previously reported on four-terminal (4T) self-aligned planar embedded metal double-gate (E-MeDG) low-temperature (LT) poly-Si TFTs on glass substrate. This device includes a metal top gate (TG) and a metal bottom gate (BG), which are fabricated from a sputtered tungsten film. The BG is embedded in the glass substrate through chemical mechanical polishing, and the TG is fabricated in a self-aligned manner to the BG by using back-surface exposure. The material of the gate dielectric is silicon dioxide (SiO2), which is deposited using plasma-enhanced chemical vapor deposition, and has a thickness of 75 and 150 nm against the TG and BG, respectively. The material of the channel region is poly-Si, which is fabricated using diode-pumped solid-state continuous-wave laser lateral crystallization. The TG and BG can be used as the drive and control gates, and vice versa. In this device, we were able to control the threshold voltage (Vth) by varying the voltage applied to the control gate, and we confirmed a high Vth controllability. This Vth controllability is applicable for pH sensors because voltage variation applied to the control gate due to a change in pH can be read as the Vthvariation of the TFTs. Therefore, the 4T self-aligned planar E-MeDG LT poly-Si TFT can be used as an extended-gate field-effect transistor (EGFET) to measure the voltage variation due to a change in pH. Thus, we performed an evaluation of pH sensors by using the 4T self-aligned planar E-MeDG LT poly-Si TFT as an EGFET. The evaluation of pH sensors was performed using a typical glass electrode, reference electrode, and pH buffer solution in addition to the 4T self-aligned planar E-MeDG LT poly-Si TFTs. The glass electrode was connected to the TG or BG of the TFTs. The reference electrode was connected to the electrode, which applied a constant voltage. The glass electrode and reference electrode were set in the pH buffer solution. In this situation, we evaluated the pH sensors by measuring the transfer characteristics of the TFTs by using another gate, which was not connected to the glass electrode, as the drive gate. In the first experiment, we connected the glass electrode to the BG and measured the transfer characteristics by using the TG as the drive gate against pH = 8.8 and pH = 4.2 buffer solutions under various reference electrode voltages. We confirmed that the transfer characteristics of the drive gate in the pH = 8.8 buffer solution shifted toward the positive direction against the characteristics in the pH = 4.2 buffer solution at every reference electrode voltage. The pH sensitivity calculated from the Vthvariation is 21.7 mV/pH, which is fairly consistent with the theoretical pH sensitivity of 25.5 mV/pH. In the second experiment, we connected the glass electrode to the TG and measured the transfer characteristics by using the BG as the drive gate against pH = 8.7 and pH = 4.8 buffer solutions at various reference electrode voltages. We confirmed that the transfer characteristics of the drive gate in the pH = 8.7 buffer solution shifted toward the positive direction against the characteristics in the pH = 4.8 buffer solution. This trend is the same as that of the top-gate drive TFT, but the pH sensitivity calculated from the Vthvariation is 76.9 mV/pH, which is larger than that of the top-gate drive TFT. In addition, its magnitude is found to be fairly consistent with the theoretical pH sensitivity of 88.8 mV/pH. We consider that the difference in pH sensitivity between the TG and BG drives is caused by the difference in thickness between the TG and BG SiO2 dielectric. We previously confirmed that the ratio of the Vthvariation against the control gate voltage variation is larger in the BG drive than in the TG drive. We consider that the difference in pH sensitivity reflects this phenomenon. Thus, the experimental results indicate that 4T self-aligned planar E-MeDG LT poly-Si TFTs can be successfully operated as pH sensors. In summary, we confirmed that 4T self-aligned planar E-MeDG LT poly-Si TFTs can be successfully operated as pH sensors. In addition, to improve the pH sensitivity of EGFETs, our experimental results indicate that the combination of the capacitance of the top and bottom gates is a significant parameter.

(Invited) Self-Aligned Four-Terminal Low-Temperature Polycrystalline-Silicon Thin-Film Transistors on Glass Substrate Using Continuous-Wave Laser Lateral Crystallization

Low-temperature (LT) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) are indispensable for applications that involve integrating high-speed and low-power dissipation complementary metal-oxide-semiconductor (CMOS) circuits onto a glass substrate. The on-current of the LT poly-Si TFTs can be enhanced by fabricating a high-quality poly-Si film on the glass substrate. In the current study, the fabrication of these transistors was achieved using continuous-wave laser lateral crystallization (CLC). This method enabled us to form a lateral poly-Si film with high quality and large grain size (the grain area was approximately 100 times larger than that of the conventional excimer-laser crystallization (ELC) poly-Si film) without damaging the substrate. A possible approach to achieve low-power dissipation is by controlling the threshold voltage (Vth). In order to control the Vth of the LT poly-Si TFTs, we fabricated self-aligned four-terminal (4T) LT poly-Si TFTs using high-quality CLC poly-Si film. These TFTs comprise metal gates on the top and bottom. The bottom metal gate was embedded in the glass substrate using a chemical mechanical polish. The top metal gate was fabricated by a self-aligned process of back surface exposure using the bottom metal gate as a photomask. This TFT was fabricated on a fused quartz glass at 550°C. The top and bottom metal gates acted as drive and control gates, respectively, or vice versa. The performance of the fabricated n-channel (n-ch) and p-channel (p-ch) self-aligned 4T CLC LT poly-Si TFTs was evaluated. To evaluate their feasibility, an E/D inverter was utilized by connecting two identical n-ch TFTs on different glass substrates, which were fabricated by identical processes.The self-aligned 4T CLC LT poly-Si TFTs showed excellent Vth controllability. The variation of the Vth of the drive gate TFT, with respect to small variation in the control gate voltage, was found to closely match the theoretically predicted values of the top and bottom gate drives for both n- and p-ch TFTs. The output characteristics of the drive TFTs were found to be sensitive to the varying magnitude of the control gate voltage. The mobility of the n-ch TFTs in the top and bottom drive TFTs was above 300 cm2/Vs. This remarkable performance may be attributed to the high-quality CLC poly-Si film. The mobility varied sensitively against the strength of the vertical electric field, which was changed by varying the control gate voltage. The s.s. values were also found to vary depending on the control gate voltage, and this variation is explained by the change in the position of the channel layer towards the side of either the drive or the control gate. By exploiting the high controllability of the 4T TFTs, an E/D inverter was fabricated and successfully operated at 2.0 V. The Vth of the self-aligned 4T CLC LT poly-Si TFTs was found to be sensitive to a 20-meV variation of the control gate voltage. Utilizing this sensitivity, we further fabricated an extended-gate pH sensor, where the control gate was connected to the glass electrodes, and the pH of the solution varied from 4.1 to 8.8. Consequently, we were able to successfully observe the variation of the drain current in the drive gate TFT depending on the strength of pH. In summary, the results suggest that the high controllability of the self-aligned 4T CLC LT poly-Si TFTs could enable us to fabricate high-speed and low-power-dissipation circuits on a glass substrate. Further, our study suggests the promising potential of such TFTs for applications involving sensor fabrication.

(Invited) The Compact Models and Parameter Extraction for Thin Film Transistors

The challenge in the compact modeling of Thin Film Transistors (TFTs) is to accurately reproduce all regimes of operation (leakage, subthreshold, and above threshold) and account for short channel and non-ideal effects. The models should be suitable for the device characterization and parameter extraction. The non-ideal effects (which might be specific to a particular TFT type) include mobility degradation at high gate biases, velocity saturation (in poly-Si TFTs), drain-induced barrier lowering, self- heating, effects of the series resistance, and the floating-body effects. The self-heating and kink effects might become important in short channel devices [1]). The unified and universal charge control models [2] that describe both the above and below threshold characteristics with one generalized charge control equation are the basic FET models that have the advantages of a better convergence (avoiding the binning problem) and a relatively small number of parameters (simplifying the parameter extraction). These models have been augmented with the AC models that account for the RC constants represented by the fractions of the channel resistances in series with the gate-to-source and gate-to-drain capacitances for reproducing the frequency dispersion. The non-linear contacts have been modeled as non-linear transmission lines and/or non-ideal diodes. [3] Such compact TFT models have been implemented in circuit simulators [3] and, with certain modifications, they are suitable for the simulation of amorphous Si, poly-Si, monocrystalline silicon, and even organic TFTs. [4] [1] L. Wang, T.A. Fjeldly, B. Iniguez, and M.S. Shur, Self-heating and Kink Effects in a-Si:H Thin Film Transistors, IEEE Trans. Electron Devices, Vol. 47, p. 387, February 2000 [2] T. A. Fjeldly, T. Ytterdal and M. Shur, `Introduction to device modeling and circuit simulation,' Wiley, NY 1997. [3] B. Iniguez, L. Wang, Z. Xu, T.A. Fjeldly and M.S. Shur, Short Channel AIM-Spice Models for Amorphous and Polysilicon Thin Film Transistors, in Future Trends in Microelectronics. The Road Ahead, John Wiley and Sons, 1999, p. 213 [4] P.V. Necliudov, M.S. Shur, D.J. Gundlach, T.N. Jackson, Modeling of organic thin _lm transistors of different designs, J. Appl. Phys., December 15 (2000) Figure 1

Charge-Trap Inactivation of Multi-Line-Beam Clc Poly-Si Tfts Using Channel Impurity Doping

Linearly-arranged long silicon crystal grains have been formed by using Multi-Line-Beam Continuous-wave laser Lateral Crystallization (MLB-CLC). Crystallinity of the laser-crystallized poly-Si thin film are biaxially oriented to (110)-(111)-(211) crystal orientation. The low-temperature poly-Si thin film transistors (LTPS-TFTs), however have a high-OFF leakage current and ON/OFF ratio become small. Charge traps on the long grain boundaries between source and drain would induce the high-OFF leakage current. In this work, we introduce a channel doping for inactivation of the traps, and high ON/OFF ratio is achieved. Poly-Si TFTs were fabricated as follows. Buffer SiO2 film (1 μm), a-Si (150 nm) and cap SiO2 (100 nm) were deposited on a quartz substrate. CW laser lateral crystallization with multi-line laser-beam spot was carried out on the a-Si films. The wavelength of the laser was 532 nm, and laser power and scan speed were 7.5 W and 0.5 cm/s, respectively. After the laser crystallization, the cap SiO2 was etched with buffered HF aqueous solution (BHF). In order to pattern the poly-Si active layer, lithography and dry etching (Cl2: 20 sccm, HBr: 20 sccm) were performed. Channel doping on channel region was carried out by boron (B) ions with 3 conditions (ion dose: 5×1012 cm-2, 7×1012 cm-2, 9×1012 cm-2, acceleration voltage: 19 keV). Gate SiO2 (42 nm) was deposited with ICP- CVD. Mo gate electrode (300 nm) was deposited by sputtering method. After resist patterning, the gate electrode was etched with an aqueous solution of H3PO4: HNO3: CH3COOH: H2O = 400: 25: 50: 25. A self-aligned S/D regions were formed by As ion doping (ion dose: 2×1015cm-2, acceleration voltage: 66 keV). Activation anneal was carried out at 550℃ in N2 ambient for 30 minutes. A sacrificial oxide layer in the S/D region was removed with BHF. After the removal, interlayer SiO2 film was deposited with APCVD. Contact holes were formed on the APCVD interlayer dielectric film with BHF. Mo metal pad was deposited by sputtering method, and finally the samples were sintered at 400°C in H2 ambient for 30 minutes. The IDS - VGS characteristic of the fabricated poly-Si TFTs are shown in Fig.1. As the boron impurity concentration increased, the off-leakage current was reduced. It is considered that boron impurity compensated the defect traps in the channel region. At the concentration of 1.3×1020 cm-3, the off leakage current at Vg=0 V was 3×10-11 A and ON/OFF ratio was 106. ON current was reduced by introducing the channel impurity. The electron field-effect mobilities for the boron impurities of 7.1×1019 cm-3, 1.0×1020 cm-3 and1.3×1020 cm-3 were 398, 333, and 261 cm2/Vs, respectively. By introducing boron impurity, the Coulomb scattering was occurred and the electron mobility was reduced. Figure 1

Characterization of (100)-Dominantly Oriented Poly-Si Thin Film Transistors Using Multi-Line Beam Continuous-Wave Laser Lateral Crystallization

(100)-dominantly oriented poly-Si film was realized by using multi-line beam (MLB) continuous-wave laser lateral crystallization (CLC) with overlapping. Si grains were developed along laser scanning direction with an average grain size of approximately 20 μm x 2 μm. The fabricated TFTs have high field effect mobility up to 1010 cm2/Vs. In this work, the device characteristics of the fabricated TFTs are investigated. Fabrication process of the poly-Si TFTs are as follows: A buffer SiO2 layer of 1 μm thickness was deposited on a quartz substrate by Plasma-Enhanced Chemical Vapor Deposition (PECVD). Sequentially, an amorphous Si (a-Si) film of 150 nm thickness and a cap SiO2 of 100 nm thickness were deposited by PECVD. The films were dehydrogenated by furnace annealing at 490 oC in N2 ambient for an hour before crystallization with MLB-CLC (wavelength: 532 nm, laser power: 6 W). The laser beams scanned the sample at a speed of 0.8 cm/s with an overlapping ratio of 83%. After the cap SiO2 layer was etched by buffered hydrofluoric acid (BHF) solution, the poly-Si active layer was patterned using lithography and dry etching (Cl2: 20 sccm, HBr: 20 sccm). Gate oxide SiO2 of 42 nm thickness was deposited by Electron cyclotron Resonance (ECR) Plasma Chemical Vapor Deposition (SiH4: 0.6 sccm, O2: 10 sccm, Ar: 40 sccm) and Mo gate electrode of 300 nm thickness was deposited by sputtering. Patterning gate electrodes was carried out by lithography and wet etching (H3PO4:HNO3:CH3COOH:H2O = 400:25:50:25), followed by self-aligned source and drain formation by As ion implantation (ion dose: 2 x 1015 cm-2, accelerating voltage: 66 kV) using the Mo gate as mask. Activation annealing treatment was performed at 550 oC in N2 ambient for 30 minutes. Before SiO2 insulator film of 600 nm was deposited by Atmospheric Pressure Chemical Vapor Deposition (APCVD), sacrificial SiO2 in source and drain region was etched by BHF. Contact hole was formed by lithography and BHF wet etching. Mo metal pad of 700 nm thickness was deposited by sputtering and patterned by lithography and wet etching. Finally, the sample was annealed at 400 oC in H2 ambient for 30 minutes. The highest temperature of the fabrication processes was 550 oC. The devices were designed with the width and length of channel of W = 10 µm and L = 10 µm, respectively. Figure 1 shows microphotograph of poly Si film and schematic of TFT designed mask. This result reveals that poly-Si film was periodic in 200 µm and the channels were fabricated parallel with scanning direction in 10 groups at different positions. In particular, TFTs of group 1 were fabricated along heavy-void regions and distance of two consecutive groups was 20 µm in perpendicular direction of laser scan. Figure 2 shows an EBSD mapping of the laser-crystallized poly-Si films. It was found that (100) Si crystal grains with an average size of 20 µm x 2 µm were formed. In this figure, crystal orientation of the poly-Si film was different from the middle to the side of the measured region. As result, characteristics of TFTs was relatively different in each group. Table I indicates average mobility, maximum mobility, and variation of TFTs in 10 groups. TFTs with ultrahigh electron field effect mobility (µFE ) of over 1000 cm2/Vs in a linear region was realized. A high average electron field effect mobility of 636 cm2/Vs and its low variation of 25% were achieved in group 7 in which (100) Si crystal grains were dominant. Figure 3 shows IDS-VGS characteristics of poly Si TFTs in group 7. A high off-leakage current and its high variation of 10-10 – 10-6 were observed owing to trap states in both the grain boundaries and crystal grains. Table I.Average mobility of TFTs and their variation in each group Group Average mobility (cm2/Vs) Maximum mobility (cm2/Vs) Standard deviation (cm2/Vs) 1 2 3 4 5 6 7 8 9 10 270 490 453 476 510 590 636 600 632 618 512 1010 780 717 697 873 971 940 973 808 114 264 131 148 79 167 159 194 183 118 Figure 1

(Invited) Self-Aligned Four-Terminal Low-Temperature Polycrystalline-Silicon Thin-Film Transistors on Glass Substrate Using Continuous-Wave Laser Lateral Crystallization

To integrate circuits on a glass substrate, high-performance and low-power-dissipation low-temperature (LT) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) are indispensable. Fabrication of high-quality poly-Si film is one approach to enhance the on-current of LT poly-Si TFTs on a glass substrate. In this paper, we used continuous-wave laser lateral crystallization (CLC) to fabricate high-quality lateral large-grained poly-Si films on a glass substrate. To achieve low power dissipation, threshold voltage (Vth) control technology is one tentative approach. To control the Vth of LT poly-Si TFTs, we fabricated four-terminal (4T) self-aligned embedded metal double-gate (E-MeDG) LT poly-Si TFTs using high-quality CLC poly-Si films. The 4T self-aligned E-MeDG CLC LT poly-Si TFTs showed excellent Vth controllability. By exploiting the high controllability of the 4T TFTs, E/D inverter and extended gate pH sensor were fabricated and successful operation with high performance was confirmed.

Characterization of (100)-Dominantly Oriented Poly-Si Thin Film Transistors Using Multi-Line Beam Continuous-Wave Laser Lateral Crystallization

Low-temperature poly-Si thin film transistors with high mobility and uniformity have been required for high resolution flat panel display (FPD) technology. In this work, we succeeded in controlling orientation of poly-Si film by using multi-line beam (MLB) continuous-wave laser lateral crystallization (CLC) with overlapping and (100)-dominantly oriented poly-Si film was realized. Si crystal grains were developed along laser scanning direction with an average grain size of approximately 20 μm x 2 μm. The adjacent Si crystal grains had almost identical orientation in the space with misorientation angle of under 15o. The fabricated TFTs have high field effect mobility up to 1010 cm2/Vs. Moreover, device characteristics of the fabricated TFTs were investigated and mobility variation was evaluated.

Microsecond Crystallization of Amorphous Silicon Films on Glass Substrates by Joule Heating

Joule-heating-induced crystallization (JIC) of amorphous silicon (a-Si) films was conducted by applying an electric pulse to a conductive layer located beneath or above the films. Crystallization occurs across the whole substrate surface within few tens of microseconds. The phase-transformation phenomena during the JIC process were detected electrically and optically by the in-situ measurements of input voltage/current and normal reflectance at wavelength of 532 nm. We devised a method for the crystallization of a-Si films while preventing arc generation; this method consisted of pre-patterning an a-Si active layer into islands and then depositing a gate oxide and gate electrode. Electric pulsing was then applied to the gate electrode formed using a Mo layer. JIC-processed poly-Si thin-film transistors were fabricated successfully, and the proposed method was found to be compatible with the standard processing of coplanar top-gate poly-Si TFTs.

Electrical Properties of Bottom Gate Poly-Si TFTs by NiSi2 Seed-Induced Lateral Crystallization and Its Applications

ABSTRACT In this paper, the electrical properties of bottom-gate (BG) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) by NiSi2 seed-induced lateral crystallization (SILC) and its applications are presented. Sequential lateral solidification (SLS), which is one of crystallization methods, is known to have poor electrical properties of TFTs with BG structures due to problems induced by laser. Therefore, the laser method cannot be used to well-developed production line of amorphous-Si (a-Si) TFT, resulting in large initial investment cost to change fabrication procedures. On the other hand, the BG poly-Si TFT by SILC (SILC-BGPS TFT) has basically compatible process flows with that of the a-Si TFT. The SILC-BGPS TFT exhibited threshold voltage of -3.9 V, steep subthreshold slope of 130 mV/dec, a high field-effect mobility of 129 cm2/Vs , and I on /I off ratio of ∼106.

Reduction of Kink Effect of Poly-Si TFT With Bottom Field Plate by Dispersing Current Density Technique

A new multiple-gate poly-Si thin-film transistor (TFT) with a bottom field plate (FP) is proposed. The FP disperses the high current density away from the top corner of the spacer channel with the highest electric field, leading to an improved kink effect. Moreover, owing to an inversion layer induced by the FP at the bottom region of spacer poly-Si channel, a higher on-state current is achieved. In addition, the electric field near drain area is reduced, leading to a lower off-state current. Overall, the new multiple-gate poly-Si TFT shows improved characteristics as compared with the counterpart without a bottom FP.

Erratum to: Progress of p-channel bottom-gate poly-Si thin-film transistor by nickel silicide seed-induced lateral crystallization

Excimer laser annealing (ELA) is known to be the most common crystallization technology for the fabrication of low-temperature polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) in the mass production industry. This technology, however, cannot be applied to bottom-gate (BG) TFTs, which are well developed for the liquid–crystal display (LCD) back-planes, because strong laser energy of ELA can seriously damage the other layers. Here, we propose a novel high-performance BG poly-Si TFT using Ni silicide seed-induced lateral crystallization (SILC). The SILC technology renders it possible to ensure low damage in the layers, smooth surface, and longitudinal large grains in the channel. It was observed that the electrical properties exhibited a steep subthreshold slope of 110 mV/dec, high field-effect mobility of 304 cm2/Vsec, high Ion/Ioff ratio of 5.9 × 107, and a low threshold voltage of −3.9 V.

Progress of p-channel bottom-gate poly-Si thin-film transistor by nickel silicide seed-induced lateral crystallization

Progress of p-channel bottom-gate poly-Si thin-film transistor by nickel silicide seed-induced lateral crystallization

A Frequency-Dependent Capacitance–Voltage Model for Thin-Film Transistors

A frequency-dependent capacitance–voltage (CV) model is developed for thin-film transistors (TFTs). The model includes not only a static CV model for channel charge analysis and a transmission line method for $RC$ delay effect but also the frequency-dependent trapped charges effect on the measured capacitance. The complete model based on the same set of model parameters is verified by the measured CV characteristics of top-gated self-aligned poly-Si TFTs with varied frequencies from 10 kHz to 1.5 MHz for two devices of different channel lengths, and at both room temperature and an elevated temperature of 100 °C.

Fabrication of High-Performance Bridged-Grain Polycrystalline Silicon TFTs by Laser Interference Lithography

In this paper, bridged-grain (BG) low-temperature polycrystalline silicon thin-film transistors (TFTs) were fabricated. The periodic submicrometer BG structures were patterned using a maskless and large-area applicable laser interference lithography (LIL) technology, which was able to minimize extra manufacture costs of BG structures. Compared with conventional metal-induced crystallized (MIC) poly-Si TFTs, the BG-MIC TFTs involving the LIL technology exhibited reduced threshold voltage and subthreshold swing, improved ON–OFF current ratio, and suppressed leakage current and kink effect. Since the exposure energy density is one of key parameters for LIL, its relationship with device electrical performance was further investigated. It was found that when the exposure energy density was in the vicinity of 60 mJ/cm2, these BG-MIC TFTs could perform optimally without device uniformity degradation.

Lateral Grain Growth of Amorphous Silicon Films With Wide Thickness Range by Blue Laser Annealing and Application to High Performance Poly-Si TFTs

We report high performance p-type poly-Si thin-film transistors (TFTs) achieved by lateral grain growth of amorphous silicon (a-Si) by using a continuous-wave blue diode laser of wavelength 445 nm. The blue laser beam is efficiently absorbed into the a-Si film, such that full melting and lateral crystallization is achieved in all thicknesses investigated, 50-200 nm. TFTs fabricated with 75-, 100-, and 125-nm-thick poly-Si films laterally grown by the blue laser annealing exhibited field-effect mobility of 108 ± 7, 104 ± 9, and 134 ± 12 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V · s, and subthreshold swing of 210±51, 191±16, and 193±53 mV/decade, respectively, and high ON/OFF current ratio of ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> .

Controllability of self-aligned four-terminal planar embedded metal double-gate low-temperature polycrystalline-silicon thin-film transistors on a glass substrate

Self-aligned four-terminal n-channel (n-ch) and p-channel (p-ch) planar embedded metal double-gate polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) were fabricated on a glass substrate at a low temperature of 550 °C. This device includes a metal top gate (TG) and a metal bottom gate (BG), which are used as the drive and control gates or vice versa. The BG was embedded in a glass substrate, and a poly-Si channel with large lateral grains was fabricated by continuous-wave laser lateral crystallization. The threshold voltage modulation factors under various control gate voltages (γ = ΔVth/ΔVCG) were nearly equal to the theoretical predictions in both the n- and p-ch TFTs. By exploiting this high controllability, an enhancement depletion (ED) inverter was fabricated, and successful operation at 2.0 V was confirmed.

Carrier transport across grain boundaries in polycrystalline silicon thin film transistors

We established a model for investigating polycrystalline silicon (poly-Si) thin film transistors (TFTs). The effect of grain boundaries (GBs) on the transfer characteristics of TFT was analyzed by considering the number and the width of grain boundaries in the channel region, and the dominant transport mechanism of carrier across grain boundaries was subsequently determined. It is shown that the thermionic emission (TE) is dominant in the subthreshold operating region of TFT regardless of the number and the width of grain boundary. To a poly-Si TFT model with a 1 nm-width grain boundary, in the linear region, thermionic emission is similar to that of tunneling (TU), however, with increasing grain boundary width and number, tunneling becomes dominant.

Effects of Solid Phase Crystallization Condition and Gate Insulator Thickness on Device Properties of Poly-Si Thin Film Transistors

Effects of Solid Phase Crystallization Condition and Gate Insulator Thickness on Device Properties of Poly-Si Thin Film Transistors