Performance dependence of self-aligned dual-gate poly-Si TFTs on localized defective regions

Abstract

This study investigates effects of localized defect regions on electrical characteristics of self-aligned dual-gate poly-Si thin-film transistors (TFTs). The thickness of the poly-Si channel layer ranges from 20 nm to 140 nm. The threshold voltage, subthreshold swing, and mobility are found to be sensitive to the defect position. The localized defects in the left channel (source side) exhibit a significant impact while those in the right channel (drain side) show a lower influence on the TFT performance. In addition, the performance variation caused by the localized defects in the right channel is highly sensitive to the magnitude of the applied drain bias. A higher drain bias can observably reduce the performance degradation. Effects of multiple defect regions on the electrical behavior of the TFTs are also explored. We found that the upper width of the defect regions dominates the TFT performance deterioration. The hole transport, hole concentration distributions, and current flowlines are analyzed to study the physical mechanisms.