Device Instability Under High Gate and Drain Biases in InGaZnO Thin Film Transistors

Abstract

An experimental investigation of channel-hot-carrier-induced device degradation in indium-gallium-zinc oxide (IGZO) thin-film transistors was undertaken for different stress biases and channel widths. Although there is no shift of the transfer curve after only a positive gate stress, a negative shift of the transfer curve is observed after both positive gate and drain stresses. The decrease in threshold voltage and the increase in the inverse subthreshold slope are observed. The negative shift of the transfer curve may be attributed to the doubly charged oxygen vacancies generated by the injection of the channel hot electrons into the gate dielectric layer. From the measurements with different drain stresses at a constant gate stress, it was found that the device degradation occurred when the lateral electric field reaches a critical value. From device simulations and measurements, it was found that the interface trap charges are located near the source side at high gate stress voltages. On the other hand, they are located near the drain side at lower gate stress voltages. The device degradation was the most significant at the stress condition of V GS = VDS, when the stress VDS is constant. Device degradation increases with channel widths.