poly-Si TFTs Research Articles

Laser Crystallization of Silicon for Large Area Electronics

AbstractLaser crystallization of silicon is discussed for forming polycrystalline silicon thin films used to fabricate polycrystalline silicon thin film transistors (poly-Si TFTs). Laser-induced rapid heating is important for crystalline film formation with a low thermal budget. Structural and electrical properties of poly-Si films are discussed. Reduction of electrical active defects located at grain boundaries is essential for achieving poly-Si TFTs with high performances. The internal film stress is attractive to increase the carrier mobility. Recent development in laser crystallization methods with pulsed and continuous wave (CW) lasers is then reviewed. Control of the heat flow results in crystalline grain growth in the lateral direction, which is essential for fabrication of large crystalline grains. We also report an annealing method using a high power infrared semiconductor laser. High power lasers will be attractive for rapid crystallization of silicon films over a large area and activation of doped regions.

Characteristics of Pr[sub 2]O[sub 3] Gate Dielectric Thin-Film Transistors Fabricated on Fluorine-Ion-Implanted Polysilicon Films

A simple and effective scheme for fabricating high dielectric constant (high-K) praseodymium oxide (Pr 2 O 3 ) gate dielectric thin-film transistors (Pr 2 O 3 TFT) on fluorine-ion-implanted polysilicon films was proposed and demonstrated for the first time. Incorporating the fluorine-incorporation method with high-K Pr 2 O 3 gate dielectric cannot only effectively passivate the trap states in the poly-Si film but also significantly increase the gate capacitance density. With the incorporation of fluorine ions, the electrical characteristics of Pr 2 O 3 TFT can be remarkably improved, including smaller threshold voltage, steeper subthreshold swing, higher field-effect mobility, lower gate-induced drain leakage current, and better on/off current ratio. In addition, the incorporation of fluorine ions in the poly-Si film also improves the reliability of Pr 2 O 3 TFT against hot-carrier stress, which is attributed to the formation of stronger Si-F bonds. Therefore, the proposed scheme is a promising technology for high-performance solid-phase crystallized poly-Si TFTs.

Room-Temperature Sputter-Deposited Gate SiO2 Films for High Quality Poly-Si TFTs

Gate SiO2 films in poly-Si TFTs were fabricated by sputtering at substrate temperature from 300°C down to room-temperature. It was found that poly-Si TFT characteristics of mobility, threshold voltage and subthreshold slope were greatly improved by decreasing substrate temperature. Mobility of the poly-Si TFT for room-temperature was 90 cm2/V.s, much higher than 50 cm2/V.s for 300°C. Moreover, sputtered gate SiO2 poly-Si TFTs showed high reliability against hot carrier effect even for room-temperature-deposition.

High Reliability and Performance Poly-Si TFTs for System in Displays

Narrow frame size IPS-mode LCD with high resolution system-in- display have been developed utilizing hybrid laser crystallization technology: SELAX are applied to low-power, high-speed circuits, and conventional ELC are used for the high- voltage circuits. The TFT degradation phenomena under dynamic stress are clarified, and the high-immunity TFT structure and high-quality gate insulator are proposed.

The Geometry Effect of A Counter-Doped Lateral Body Terminal on Poly-Si TFTs

We have designed and fabricated poly-Si TFTs employing various counter-doped lateral body terminals (LBT) which suppress a kink current and improve the reliability under the various electrical stresses. Our experimental results show that the TFT with a LBT structure connected near the drain region was more effective to suppress the kink current and to reduce the leakage current. The suppression of the kink effect employing LBT structure can be attributed to the decrease of E-field at the drain junction due to the potential redistribution in the channel of the TFT by the counter doped LBT and the collecting holes, which have been generated by impact ionization at the drain.

The Role of Grain Boundaries on the Performance of Poly-Si TFTs

The role of grain boundaries on the performance of polycrystalline Si thin film transistors is investigated through the temperature analysis of the transfer characteristics. The investigation is performed on devices fabricated on films that consist of long grains, separated by parallel boundaries. The transport properties are studied by employing channel orientations parallel and vertical to the grain boundaries. Finally, the data analysis reveals that the major device parameters are thermally activated.

Defect Passivation in Poly-Si TFTs by Ion Implantation and Pulsed Laser Annealing

Improvement in the performance of excimer laser annealed (ELA) poly-Si thin-film transistors was seen through ion implantation of N, O, or F prior to the ELA step. Devices passivated in this way show steeper subthreshold swings, higher carrier mobilities, and lower off current than unpassivated or hydrogen-passivated devices, even in a low thermal budget process. With the addition of a higher temperature anneal, the N passivated devices are superior both in terms of performance and reliability

High-performance polycrystalline silicon thin-film transistors with oxide–nitride–oxide gate dielectric and multiple nanowire channels

This work presents a method to enhance the performance of polycrystalline silicon thin film transistors (poly-Si TFTs) by using an oxide–nitride–oxide (ONO) gate dielectric and the multiple nanowire channels structure. Experimental results indicate that the performance of the device was enhanced by using the ONO multilayer, because the ONO gate dielectric constant is increased compared to the conventional oxide gate dielectric. Additionally, the TFTs with a ten nanowire channel structure (NW-TFTs) have superior electrical characteristics compared to other TFTs. This is because a structure with more corners and a shorter radius has better gate control due to the corner effect.

Quasi-Static Capacitance–Voltage Characteristics of Polycrystalline Silicon Thin-Film Transistors

We have investigated the quasi-static capacitance–voltage (QSCV) characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs), focusing on how the integration time for the capacitance measurement affects the QSCV curves. We have found that the response time of the carriers in the OFF state of the TFTs can be estimated from the QSCV results. QSCV measurements with external illumination enable us to estimate the surface depletion capacitance of TFTs. We have also found that the QSCV characteristics vary with the channel length of TFTs, indicating that the channel length dependence must be taken into account when making a model of TFT capacitance in the OFF state.

Excimer laser recrystallization of nanocrystalline-Si films deposited by inductively coupled plasma chemical vapour deposition at 150°C

Polycrystalline silicon thin film transistors (poly-Si TFTs) fabricated at low temperature (under 200°C) have been widely investigated for flexible substrate applications such as a transparent plastic substrate. Unlike the conventional TFT process using glass substrate, the maximum process temperature should be kept less than 200°C in order to avoid thermal damage on flexible substrates. We report the characteristics of nanocrystalline silicon (nc-Si) irradiated by an excimer laser. Nc-Si precursors were deposited on various buffer layers by inductively coupled plasma chemical vapour deposition (ICP-CVD) at 150°C. We employed various buffer layers, such as silicon nitride (SiNX) and silicon dioxide (SiO2), in order to report recrystallization characteristics in connection with a buffer layer of a different thermal conductivity. The dehydrogenation and recrystallization was performed by step-by-step excimer laser annealing (ELA) (XeCl,λ=308 nm) in order to prevent the explosive release of hydrogen atoms. The grain size of the poly-Si film, which was recrystallized on the various buffer layers, was measured by scanning electron microscopy (SEM) at each laser energy density. The process margin of step-by-step ELA employing the SiNX buffer layer is wider than SiO2 and the maximum grain size slightly increased.

Dual-Gate Polycrystalline Silicon Thin-Film Transistors with Intermediate Lightly Doped Region

I have proposed and developed dual-gate polycrystalline silicon thin-film transistors (poly-Si TFTs) with an intermediate lightly doped region (LDR) for the reduction of leakage current. The proposed poly-Si TFTs are easily fabricated and have a symmetric structure less sensitive to misalignment than the conventional LDD poly-Si TFTs. In the proposed TFTs, it is proved that a decrease in leakage current is due to a reduction in lateral electric field at the drain edge and a reduction in on-current is caused by an increase in the resistance of the LDR. The leakage current of the proposed TFTs is significantly reduced and the maximum ON/OFF current ratio is obtained with a 2 µm LDR length and a 2×1013/cm2 LDR implant dose.

Electrical Enhancement of Solid Phase Crystallized Poly-Si Thin-Film Transistors with Fluorine Ion Implantation

Solid phase recrystallized polycrystalline silicon thin-film transistors (SPC poly-Si TFTs) with fluorine ion implantation were investigated in this study. Electrical characteristics and reliability of the proposed poly-Si TFTs were improved effectively, especially for field effect mobility and off current. The fluorine-ion-implanted poly-Si TFT can suppress the hot carrier multiplication near the drain side, leading to superior endurance to electrical stress compared with conventional poly-Si TFTs. It was found that fluorine ions will pile up at the poly-Si interface during thermal annealing, without the initial deposition of pad oxide. The proposed technology is manageable and compatible with conventional poly-Si TFT fabrication. As the ion dosages increase more than , however, the electrical characteristics of poly-Si TFTs were degraded due to the increase of trap state density caused by the fluorine segregation in the poly-Si film.

The Role of Grain Boundaries on the Performance of Poly-Si TFTs

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The Analysis of the Poly-Si TFTs with Counter-Doped Lateral Body Terminal

not Available.

High Reliability and Performance Poly-Si TFTs for System in Displays

not Available.

Novel L-Shaped Dual-Gate Structure of Polycrystalline Silicon Thin-Film Transistors for the Reduction of the Kink Current in Sequential Lateral Solidification or Continuous Wave Laser Method

An L-shaped dual-gate device structure, which reduces kink current in polycrystalline silicon thin-film transistors (poly-Si TFTs), has been proposed and fabricated. In the proposed device, the poly-Si TFTs have a lateral grain growth in channels such as TFTs fabricated by sequential lateral solidification (SLS) or CW laser crystallization. The current flow of dual TFTs is strongly affected by grain boundaries showing lateral grain growth. The L-shaped dual gate structure is employed for asymmetry between dual channels. One of the channels is located in a parallel direction of grain growth and the other is located vertically. It is verified by experiment that the proposed L-shaped dual-gate TFT reduced the kink current of poly-Si TFT and showed improved reliability by fixed current flow in the saturation mode.

High-performance metal-induced lateral-crystallization polysilicon thin-film transistors with multiple nanowire channels and multiple gates

In this study, pattern-dependent nickel (Ni) metal-induced lateral-crystallization (Ni-MILC) polysilicon thin-film transistors (poly-Si TFTs) with ten nanowire channels and multigate structure were fabricated and characterized. Experimental results reveal that applying ten nanowire channels improves the performance of an Ni-MILC poly-Si TFT, which thus has a higher ON current, a lower leakage current, and a lower threshold voltage (V/sub th/) than single-channel TFTs. Furthermore, the experimental results reveal that combining the multigate structure and ten nanowire channels further enhances the entire performance of Ni-MILC TFTs, which thus have a low leakage current, a high ON/OFF ratio, a low V/sub th/, a steep subthreshold swing, and kink-free output characteristics. The multigate structure with ten-nanowire-channel Ni-MILC TFTs has a few poly-Si grain boundary defects, a low lateral electrical field, and a gate-channel shortening effect, all of which are associated with such high-performance characteristics.

New Current-Scaling Pixel Circuit Compensating Non uniform Electrical Characteristics for Active Matrix Organic Light Emitting Diode

We have proposed and successfully fabricated a new serial current mirror pixel design for an active-matrix organic light-emitting diode which consists of four polycrystalline silicon thin-film transistors (poly-Si TFTs) and one capacitor. The non uniformity of OLED current (IOLED) due to the nature of a poly-Si TFT is considerably suppressed. Our experimental results show that the non uniformity of IOLED due to threshold voltage and mobility variation is around 7% whereas that of IOLED is about 25% in the conventional 2-TFT pixel. When supply voltage decreases from 10 V to 9.5 V, the non uniformity of OLED current is suppressed to 2.2% whereas that of OLED current is 35% in the 2-TFT pixel. The proposed pixel can successfully compensate the variation of the electrical characteristics of the poly-Si TFTs as well as provide uniform OLED current despite the supply voltage drop.

Sputter-Deposited Thin Gate SiO2 Films for High Quality Polycrystalline Silicon Thin Film Transistors

Polycrystalline silicon thin film transistors (poly-Si TFTs) with sputter-deposited thin gate SiO2 films down to 9.5 nm have been fabricated and characterized. High performance n- and p-channel poly-Si TFTs were obtained by using sputter-deposited gate SiO2 films. Electrical characteristics of on-current, threshold voltage and subthreshold slope were improved by thinning gate SiO2 film. It was also clarified that “punch-through” short-channel effect was effectively suppressed by thinning gate SiO2 films down to 9.5 nm. Moreover, high speed operation of complementary circuit consisted of n- and p-channel poly-Si TFTs was confirmed. In addition, sputter-deposited SiO2 films showed excellent insulating properties of high breakdown electric field and low leakage current.

Improvement of electrical characteristics for fluorine-ion-implanted poly-Si TFTs using ELC

The fluorine ion implantation applied to the polycrystalline silicon thin-film transistors (poly-Si TFTs) is investigated in this letter. Experimental results have shown that fluorine ion implantation effectively minimized the trap state density, leading to superior electrical characteristics such as high field-effect mobility, low threshold voltage, and high ON/OFF current ratio. Furthermore, the fluorine ions tended to segregate at the interface between the gate oxide and poly-Si layers during the excimer laser annealing, even without the extra deposition of pad oxide on the poly-Si film. The presence of fluorine obviously enhanced electrical reliability of poly-Si TFTs.