poly-Si TFTs Research Articles

Characterization of Poly-Si TFTs Using Amorphous SixGey for a Seed Layer

Characterization of Poly-Si TFTs Using Amorphous SixGey for a Seed Layer

A new analytical threshold voltage model for the doped polysilicon thin-film transistors

A new analytical threshold voltage model for the doped polysilicon thin-film transistors (poly-Si TFTs) is proposed in this paper, which is related to U-shaped distribution of density of states in the grain boundary, the gate oxide thickness, the substrate doping concentration, and the grain size. Moreover, the new model has a simple functional form and it can reduce to the threshold voltage model of the conventional long channel MOSFET when the grain size is large.

Laser crystallization for large-area electronics

Laser crystallization is reviewed for the purpose of fabrication of polycrystalline silicon thin film transistors (poly-Si TFTs). Laser-induced rapid heating is important for formation of crystalline films with a low thermal budget. Reduction of electrically active defects located at grain boundaries is essential for improving electrical properties of poly-Si films and achieving poly-Si TFTs with high performances. The internal film stress is attractive to increase the carrier mobility. Recent developments in laser crystallization methods with pulsed and continuous-wave lasers are also reviewed. Control of heat flow results in crystalline grain growth in the lateral direction, which is important for fabrication of large crystalline grains. We also report an annealing method using a high-power infrared semiconductor laser. High-power lasers will be attractive for rapid formation of crystalline films over a large area and activation of silicon with impurity atoms.

Modeling of kink effect in polycrystalline silicon thin-film transistors

A new analytical DC model accounting for the kink effect of polycrystalline silicon thin-film transistors (poly-Si TFTs) is presented in this paper. When considering the exponential density of trap states in the film, a quasi-two-dimensional approach is used to give an analytic expression for avalanche multiplication factor. Compared with the available experimental data, the proposed model provides accurate description of the output characteristics over a wide range of bias voltages. Based on the kink model, higher drain voltages or higher trap states density leads to higher avalanche multiplication factors.

Fabrication and characterization of low temperature polycrystalline silicon thin film transistors by ink-jet printed nickel-mediated lateral crystallization

High-performance polycrystalline silicon thin film transistors (poly-Si TFTs) were fabricated by using ink-jet printed nickel on large area glass substrates. Direct-printed Ni dots were used as a catalyst to crystallize the amorphous silicon into poly-Si for use in the channel region of TFT devices by metal-induced lateral crystallization. The fabricated poly-Si TFTs showed high field-effect mobility and on-off ratio that are comparable to the TFTs prepared using conventional semiconductor processes. The method presented here is a combination of bottom-up and top-down approaches and has a potential to be used in next generation high-performance poly-Si TFT fabrication.

Analysis of self-heating related instability in n-channel polysilicon thin film transistors fabricated on polyimide

In this work, we investigated self-heating related instability in polysilicon thin film transistors (poly-Si TFTs) fabricated on polyimide (PI) substrates. Indeed, when Joule heating becomes relevant, the temperature of the active layer can substantially rise, since the devices are fabricated on thermally insulating substrates. As a result, electrical instability is triggered and attributed to the generation of interface states, due to the Si–H bond breaking, and charge trapping into the gate insulator. In addition, by using 3-dimensional numerical simulations, coupling the thermodynamic and transport models, we analyzed the temperature distribution of the device under operating conditions and found that self-heating is more severe for devices fabricated on plastic substrates.

Improved Electrical Performance of MILC Poly-Si TFTs Using $\hbox{CF}_{4}$ Plasma by Etching Surface of Channel

In this letter, a new manufacturing method for metal-induced lateral crystallization (MILC) polycrystalline silicon thin-film transistors (poly-Si TFTs) using CF4 plasma was proposed. It was found that CF4 plasma effectively minimizes the trap-state density by etching away the top surface of MILC and passivating the trap states, leading to superior electrical characteristics such as high field-effect mobility, low threshold voltage, low subthreshold slope, low leakage current, and high ON-/ OFF-current ratio. CF4-plasma MILC TFTs also possess high immunity against the hot-carrier stress and thereby exhibit better reliability than that of conventional MILC TFTs. Moreover, the manufacturing processes are simple (without any additional thermal annealing step) and compatible with MILC TFT processes.

High-Performance Bottom-Gate TFT Fabricated by Employing SPC with Magnetically-Assisted RTA

An n-type TFT, based on the conventional a-Si TFT process, having advanced solid phase crystallization (A-SPC) with magnetically-assisted RTA has been developed on a glass substrate. Even though the A-SPC process has a temperature higher than the glass transition temperature, it showed no glass warpage but only manageable glass shrinkage, so processing on a glass substrate is possible. The n-type TFT with A-SPC process shows higher current drivability and device reliability than an a-Si TFT, which overcomes the drawbacks of a conventional a-Si TFT backplane. It also shows relatively good short-range device uniformity to solve the problem of conventional poly-Si TFTs. The n-type backplane with A-SPC technology was veri ed by manufacturing a 15-inch AMOLED panel.

High-Performance Poly-Silicon TFTs Using a High-$k$ $\hbox{PrTiO}_{3}$ Gate Dielectric

In this letter, a polycrystalline-silicon thin-film transistor (poly-Si TFT) with a high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> PrTiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gate dielectric is proposed for the first time. Compared to TFTs with a Pr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gate dielectric, the electrical characteristics of poly-Si TFTs with a PrTiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gate dielectric can be significantly improved, such as lower threshold voltage, smaller subthreshold swing, higher <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> current ratio, and larger field-effect mobility, even without any hydrogenation treatment. These improvements can be attributed to the high gate capacitance density and low grain-boundary trap state. All of these results suggest that the poly-Si TFT with a high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> PrTiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gate dielectric is a good candidate for high-speed and low-power display driving circuit applications in flat-panel displays.

Multiple Nanowire Channel Poly-Si TFTs with Defect Passivation

This work studies the NH3 plasma passivation on a novel gate-all-around poly-Si TFTs with multiple nanowire channels (GAA-MNC TFTs). The NH3 plasma passivation can effectively passivate the defects in poly-Si channel and improve the electrical performance of poly-Si TFTs. As comparison to conventional TFTs, the GAA-MNC TFTs with NH3 plasma passivation exhibit outstanding three-dimensional gate controllability and excellent electrical characteristics, which revealed a high ON/OFF current ratio (>108), a low threshold voltage, a steep subthreshold swing, and a near-free drain-induced barrier lowering. Therefore, such the high-performance GAA-MNC TFTs are very suitable for the applications in the system-on-panel (SOP) and three-dimensional (3D) circuits.

Self-Heating Effect Induced NBTI Degradation in Poly-Si TFTs under Dynamic Stress

In this work, the characteristics of a p-type polysilicon thin-film transistor (poly-Si TFT) with dynamic bias stress were investigated. The ac stress is operated with the constant drain voltage and the varying gate voltage (0 to ) to degrade the devices. There are some phenomena which cannot be completely explained by the typical negative bias temperature instability (NBTI) mechanism in the experiment. In addition to NBTI, we suggest that the self-heating effect might be involved, because the self-heating effect could raise the channel temperature and cause the dissociation of the Si–H bonds at the poly- interface due to Joule heating. The released hydrogen reacts with and causes the fixed charge in the gate oxide. Thus, the degradation of the electrical characteristics of device is mainly dominated by the self-heating-induced NBTI effect.

Improvement of Electrical Characteristics in SPC-Si TFT Employing H2 Plasma Treatment

We fabricated PMOS SPC-Si TFTs which exhibit better uniformity than ELA poly-Si TFTs, and superior electrical stability compare to a-Si:H TFTs. We applied various H2 plasma treatments on solid phase crystallized silicon (SPC-Si) active layer prior to SiO2 gate insulator deposition, in order to improve the interface of SPC-Si. When the H2 plasma treatment with 100W power of PE-CVD was applied in the SPC-Si for 5 minutes, the electrical characteristics of the fabricated SPC-Si TFT was improved. It showed VTH of -3.91V, field effect mobility of 22.68cm2/Vs and subthreshold swing of 0.64 while the VTH of the other SPC-Si TFT was larger than -5V. We also showed that the stability of SPC-Si TFT was better than that of both poly-Si TFT and a-Si:H TFT.

Etching Treatment of MILC Poly-Si TFTs Using CF4 Plasma to Improve Electrical Performance

In this study, CF4-plasma was employed to improve the electrical performance of metal-induced lateral crystallization (MILC) polycrystalline silicon thin film transistors (poly-Si TFTs). It was found that CF4-plasma minimize effectively the trap-state density during etching surface of channel, leading to superior electrical characteristics such as high field-effect mobility, low threshold voltage, low subthreshold slope, low leakage current, and high on/off current ratio.

Analysis of the Hysteresis Behavior in Poly-Si TFTs Using On-the-Fly Measurement

The hysteresis behavior in p-type poly-Si TFTs causes malfunctions in analog circuits. To analyze the hysteresis, we adopted the On-the-Fly measurement that was used in the analyses of the negative bias temperature instability of Si LSIs. We modified the measurement for poly-Si TFTs and monitored the hole trapping from the fully detrapped states in order to quantitatively evaluate the hysteresis. A TFT annealed at 550oC had smaller trapping than a TFT annealed at 490oC due to fewer Si-OH bonds.

A DLTS Study of Band Gap States in SLS Poly-Si TFTs

The experimental knowledge of band gap states density (DOS) is of major importance for the understanding of the electrical properties of poly-Si TFTs. For this reason several methods have been employed over the last three decades. Aim of the present work is to present a new approach for direct experimental determination of DOS based on the Deep Level Transient Spectroscopy (DLTS). The investigation is performed on TFTs fabricated on sequential lateral solidified (SLS) poly-Si films. The results suggest a U-shape continuous distribution of states in the band gap as expected from theoretical predictions and other experimental observations.

A Simple Model of DIGBL Effect for Polysilicon Films and Polysilicon Thin-Film Transistors

Based on charge conservation assumption, analytical models of the drain-induced grain barrier lowering effect are developed for polysilicon films by 1-D Poisson's equation and for polysilicon thin-film transistors (poly-Si TFTs) by quasi-2-D Poisson's equation. It is shown that the voltage drop at the lower barrier side is less than that at the higher barrier side for both poly-Si films and poly-Si TFTs when applying a lateral bias across the grain-boundary barrier.

Temperature Coefficient of Poly-Silicon TFT and its Application on Voltage Reference Circuit With Temperature Compensation in LTPS Process

The temperature coefficient (TC) of n-type polycrystalline silicon thin-film transistors (poly-Si TFTs) is investigated in this paper. The relationship between the TC and the activation energy is observed and explained. From the experimental results, it is also found that TC is not sensitive to the deviation of the laser crystallization energy. On the contrary, channel width can effectively modulate the TC of TFTs. By using the diode-connected poly-Si TFTs with different channel widths, the first voltage reference circuit with temperature compensation for precise analog circuit design on glass substrate is proposed and realized. From the experimental results in a low-temperature poly-Si process, the output voltage of voltage reference circuit with temperature compensation exhibits a very low TC of 195 ppm/degC , between 25degC and 125degC. The proposed voltage reference circuit with temperature compensation can be applied to design precise analog circuits for system-on-panel or system-on-glass applications, which enables the analog circuits to be integrated in the active-matrix liquid crystal display panels.

High performance poly-Si TFTs fabricated by continuous-wave laser annealing of metal-induced lateral crystallised silicon films

In this process, amorphous silicon was first transformed to polycrystalline silicon (poly-Si) using a metal-induced lateral crystallisation (MILC) process, followed by annealing with a continuous-wave laser lateral ( lambda~ 532 nm) crystallisation (CLC) with an output power of 3.8 W. MILC-CLC-TFT performed far superior to MILC-TFT. The mobility of the MILC-CLC-TFT was 293 cm 2 /Vs, which was much higher than that of MILC TFTs (54.8 cm 2 /Vs). In addition, MILC-CLC TFTs showed better device uniformity and reliability.

The Channel Length Extension in Poly-Si TFTs With LDD Structure

In this letter, the resistance of the lightly doped drain (LDD) region in n-channel polycrystalline-silicon thin-film transistors (poly-Si TFTs) was analyzed. It was found that the LDD resistance was composed of an LDD-length-dependent part and a gate-bias-dominant part. The latter was located next to the gate edge and was governed by the channel extension phenomenon with an extended length of around 0.55 mum under a 10-V gate bias. The current density distribution simulated by Silvaco ATLAS supported this severe fringing field effect. The influences of the gate bias, LDD doping level, gate oxide thickness, and LDD length on the channel extension are also investigated with Silvaco ATLAS simulation. This letter is the first report of long channel extensions in the LDD region of poly-Si TFTs. The result may significantly influence the device model in the short channel regime.

Dynamic Characteristics of Multi-Channel Metal-Induced Unilaterally Precrystallized Polycrystalline Silicon Thin-FilmTransistor Devices and Circuits

Electrical properties of multi-channel metal-induced unilaterally precrystallized polycrystalline silicon thin-film transistor (MIUP poly-Si TFT) devices and circuits were investigated. Although their structure was integrated into small area, reducing annealing process time for fuller crystallization than that of conventional crystal filtered MIUP poly-Si TFTs, the multi-channel MIUP poly-Si TFTs showed the effect of crystal filtering. The multi-channel MIUP poly-Si TFTs showed a higher carrier mobility of more than 1.5 times that of the conventional MIUP poly-Si TFTs. Moreover, PMOS inverters consisting of the multi-channel MIUP poly-Si TFTs showed high dynamic performance compared with inverters consisting of the conventional MIUP poly-Si TFTs.